Electronics > Projects, Designs, and Technical Stuff

(1/1)

I know that standalone crystals need a specific load capacitance but is this also true for oscialltor chips like this one: http://se.farnell.com/txc/7c-50-000mbb-t/osc-50-000mhz-3-3v-smd-5-0x3-2/dp/1842050

It has a specified load capacitance but I'm assuming this is just the maximum load that it can drive since the load is usually capacitive in nature (input FET gates). The crystal oscillator circuit must surely be buffered to minimize the effect of the load to a negligible level?

Balaur:
That particular device has all the required stuff inside to generate a clock signal.

The datasheet says that the maximum output load depends on the supply voltage. Ex: 5V VDD allows you to drive a load up to 50pF.
As an example, a Virtex 6 FPGA has a typical input pin capacitance of 8pF, a PIC 16F676 has 5pF and so on.

Cheers,
Dan

alm:
What's the second (first) number for output load in the datasheet, eg. 15 pF for 5V?

Balaur:

--- Quote from: alm on October 29, 2011, 12:23:25 pm ---What's the second (first) number for output load in the datasheet, eg. 15 pF for 5V?

--- End quote ---

My understanding is that the chip can drive up to 15pF @ 1.8V, up to 30pF @ 2.5V, 2.8V, 3.3V and up to 50pF @ 5V while maintaining the specified rise and fall times. What are the other numbers for, I don't know. Examples, maybe?

sub:
It might be for when it is oscillating on the third overtone as given in the row below, perhaps.