Electronics > Projects, Designs, and Technical Stuff
Oscilloscope ASIC Kickstarter instead of Open scope.
Mechatrommer:
--- Quote from: nctnico on January 14, 2020, 12:24:54 pm ---...having multiple acquisition methods, rendering traces (persistance, color grading), etc, etc, is what makes things very complicated. And all traces need to be time aligned as well....
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or maybe you were doing it wrong? ;D sorry but just curious.. care to tell what DSO project you are talking about, so maybe we can have a look. multiple acq is like multiple lanes? multiple entry points to a mcu? is color grading and signal alignment are done in mcu too? how can a mcu possibly overlay 500KWfm/s realtime? cant FPGA be made to do such heavy task (color grade and alignment) and output its data to mcu using serial protocol i2c or some sort? parallel if necessary? or fashion it so it will make SW guy's job much easier?
--- Quote from: nctnico on January 14, 2020, 12:24:54 pm ---The oscilloscope manufacturers usually don't get it right the first time.
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should we call them inexperienced? ;D
--- Quote from: nctnico on January 14, 2020, 12:24:54 pm ---No. Look at all the oscilloscope manufacturers. They have a universal software stack which they can tailor to specific hardware. If you are going to develop the software for a very specific target it will become obsolete very quick.
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i'm imagining any HW using the SW stack must be compliant to the stack as well. there must be communication protocol that must be adhered to, no? who made the SW stack? i'm guessing they must be really experienced. we once read about "reusability" in SW. but thats just for a brief moment in time.
nctnico:
--- Quote from: Mechatrommer on January 14, 2020, 01:24:06 pm ---
--- Quote from: nctnico on January 14, 2020, 12:24:54 pm ---...having multiple acquisition methods, rendering traces (persistance, color grading), etc, etc, is what makes things very complicated. And all traces need to be time aligned as well....
--- End quote ---
or maybe you were doing it wrong? ;D sorry but just curious.. care to tell what DSO project you are talking about, so maybe we can have a look. multiple acq is like multiple lanes? multiple entry points to a mcu? is color grading and signal alignment are done in mcu too? how can a mcu possibly overlay 500KWfm/s realtime? cant FPGA be made to do such heavy task (color grade and alignment) and output its data to mcu using serial protocol i2c or some sort? parallel if necessary? or fashion it so it will make SW guy's job much easier?
--- End quote ---
I never published anything (except for my current avatar picture on the left). Remember that my project is very old. I used two spartan3 FPGAs and a standard PC style DDR memory module to get a total memory bandwidth of 1GB/s. Nowadays you just get a DDR memory interface from a hard-IP block but back then I had to develop my own from scratch. In my design the FPGA is modular and allowed to pipe the acquired (10 bit) data to memory and to post-processing modules. This -for example- allows to look at the same signal using different timebase / trigger settings and/or extremely high update rates in parallel. Scrolling through memory (playback) works in a similar way. Instead of realtime data the data is streamed from memory into the post processing modules. The memory also stores the data in formatted frames (IIRC with a timestamp) which allows -for example- to mix signal data, digital input data and decoded data in the same stream. Not saying I would use this method in a new design again but it is very flexible. The high memory bandwidth makes fetching data very quick.
The computer receives data frames which can then be converted into visible data. The whole idea hinges on the fact that having 1000 to 2000 screen pixels of width doesn't need to transfer a whole lot of data and thus keeps a reasonable update speed (5 times per second IIRC) over a low bandwidth link (like the 12Mbit/s USB 1.0 offers).
Nowadays it would be interesting to dump the acquired data into a GPU (from a SoC) and have the GPU do most of the formatting work.
excitedbox:
I have done a lot of research in the last 2 days into how much it costs to have a ASIC manufactured and designed. I like Dave“s suggestion of doing a cost analysis of the parts but I think on any scope, salaries are going to play a much larger role than parts. I will try to price out the parts needed for a scope though.
Anyone else interested in participating and dedicating some hours to this project? Please contact me with some details so we can get something official started.
As Dave has said; if this is going to work it needs to offer something that is not available now. Xilinx and Intel own all the Patents on FPGAs so we would only be able to buy an FPGA from them and design another open source oscilloscope. If you want to make yet another open source oscilloscope, I think you should start a separate project because this is about designing an ASIC.
Our job is to organize Companies, Sponsorships, Partner agreements to come up with the funds to do this and to develop an SDK. After the design and tape out is done and we have working samples we can organize a Kickstarter for a production run. So people who want to buy their own chip to use in a project can do that.
The ONLY way this can succeed though is if we can become a serious project though and this back and forth on an open forum has done nothing but put this project to negative respectability. So again, anyone that wants to actually make this happen contact me or join the discord.
PS: Manufacturer rebates is how contract discounts and free samples are handeled. Linus from LTT explained it in a video about Intel dropping prices. Basically the manufacturer gives back the cost of the parts.
Marco:
I don't see why you need field programmable logic, they are just a convenient way of connecting ADCs to memory when you use COTS ICs. For a digitizer ASIC just connect the ADC to the memory with fixed function logic, no FPGA needed ... just a license for a DDR3/4 macro or a couple thousand more expert man hours.
ogden:
--- Quote from: Marco on January 14, 2020, 06:56:12 pm ---I don't see why you need field programmable logic, they are just a convenient way of connecting ADCs to memory when you use COTS ICs.
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FPGA fabric does *everything* with waveform from ADC till LCD display (persistence, triggering and so on). How else modern FPGA-based scopes achieve >=30000 waveform updates per second? Using ARM CPU? :-DD
[edit0] In case you think someone offered to use ASIC *and* FPGA - you are mistaken.
[edit1] I think this is where OP is completely missing actual complexity of scope ASIC because it must do virtually *everything* that defines scope. If you find that you did not include something important into your design which in result means Owon and Rigol will not be your customers soon - blame yourself when investors will be coming to kill you.
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