there are top down type design, and there are called bottom up design. what i think nctnico trying to say is we start with FPGA design, let it receive some input, store it somewhere, do the triggering and output some data, and see how fast can it go... but then (to my knowledge) we also will need either to simulate the IO, or provide the suitable device to send and receive the data from the "FW". assuming the FPGA now can get 20Gbps throughput, then what? sooner or later the HW will expand to the real thing. ok maybe the GSps ADC can be replaced with Gbps FPGA to output some simulated or random data to the main FW/FPGA, and then stored in array of RAM etc, and output the 500KWfm/s data to the display. this we can call a demo platform to show that it can be done, that is phase one. costing of the complete system BOM can comes later in phase two, but it should be realistic depending on how cheap they can be mass ordered. now we can share knowledges if someone have a chap or factory next door that can source the parts at lowest price, and the logistics and all. then goes to the Kickstarter.. but i bet, the high end GHz GSps spec is not going to be cheap, maybe say 1-5K$, depending on how you see it, some people may say its better than 45K$ of mainstream brands... without the base (demo) platform to show, we can talk empty wind forever.