Electronics > Projects, Designs, and Technical Stuff
Oscilloscope ASIC Kickstarter instead of Open scope.
<< < (32/37) > >>
David Hess:

--- Quote from: Mechatrommer on January 14, 2020, 07:14:06 am ---
--- Quote from: David Hess on January 14, 2020, 06:04:32 am ---The low impedance part of the signal path is much easier than the high impedance part because the later requires a good substrate which does not suffer from excessive hook.  This is why you find high quality oscilloscopes with plastic substrates for the high impedance attenuators and modern DSOs and high voltage differential probes with bad transient response after a couple years because the FR4 substrate they used absorbed water.
--- End quote ---

lecroy 50 ohm scope has add-on adapter called AP-1M, to provide high impedance measurement, you can search eevblog i posted the internal of it, but only to few hundreds MHz BW. for GHz BW high impedance? :scared: i never seen one and not have a plan to even think about it. otherwise, i will have a very serious time (and probably financial) damage into it. but i think whats the point of trying hard to design HBW HiZ circuit when we can have or design active probe or such an AP-1M adapter in the next project phase?

the AP-1M doesnt have special ASIC nor fancy ICs, only BJT/FET discreetes, but LeCroy charge them like K$, its like nuts when thinking about it. but when think further, they probably need to gather $ from surrounding ecosystem that they have introduced, to cope with ASIC damaged they experienced on the DSO side. this is i guess how they keep going..
--- End quote ---

LeCroy is not the only one to make something like that for converting a 50 ohm input to a high impedance input suitable for high impedance passive probes.  They are also built for RF test gear like spectrum analyzers and network analyzers.  Internally an oscilloscope with high impedance inputs has the buffer like you describe built in.

High impedance active probes perform the same function as the high impedance buffer at the input of an oscilloscope with 1 megohm inputs.  Both buffer a high input impedance to drive a low impedance which is typically 50 ohms.  The difference is that the input fixture of the oscilloscope limits how low the input capacitance can be which limits bandwidth so typically 500 MHz is about the maximum while an active probe with much lower input capacitance can provide several GHz of bandwidth.  I think HP/Agilent/Keysight made some oscilloscopes with extra low input capacitance which were 700 MHz or 1 GHz?

There is also another trade-off with bandwidth.  Higher frequency JFETs and MOSFETs which have lower input capacitance have both higher flicker noise and higher broadband noise.  So achieving a low noise high impedance front end conflicts with high bandwidth.  This can be seen in older specialized oscilloscopes which had like 1 or 5 MHz of bandwidth and higher input capacitance, like 47 picofarads, but usable sensitivity down to 10s or 100s of microvolts per division.  Even lower noise high impedance front ends found in lower frequency instruments can have 100s of picofarads of input capacitance.


--- Quote from: Marco on January 14, 2020, 06:56:12 pm ---I don't see why you need field programmable logic, they are just a convenient way of connecting ADCs to memory when you use COTS ICs. For a digitizer ASIC just connect the ADC to the memory with fixed function logic, no FPGA needed ... just a license for a DDR3/4 macro or a couple thousand more expert man hours.
--- End quote ---

An FPGA is actually a pretty convenient way to interface a fast digitizer to bulk memory but there are other needed functions between the digitizer and memory like:

1. Decimation to adjust the sample rate.  The sampling clock is almost always fixed for performance reasons so decimation is used instead.
2. Digital triggering if used.
3. Acquisition modes like peak detection and high resolution.
ogden:

--- Quote from: David Hess on January 14, 2020, 11:16:21 pm ---An FPGA is actually a pretty convenient way to interface a fast digitizer to bulk memory but there are other needed functions

--- End quote ---
Yes indeed. FPGA gives flexibility. It is said million times here already - that hobbyists, "tinkerers" and open source community do not need fixed solutions like ASICs, they need something THEY can change & improve. This is what rephrasing OP's words, he seem to not understand and have no interest in learning.
Mechatrommer:

--- Quote from: excitedbox on January 14, 2020, 07:45:19 pm ---That is the point of an ASIC it is a F1 car compared to a Porsche.

--- End quote ---
most members here knows this basic fact, even i who have zero FPGA/ASIC experience. some of them cook FPGA for their life. so are you basically asking backers to pay for F1 cost? or how much fraction from it? good luck asking for Porche cost. once your "module" is completed and shipped to backers, then what? what they have to add to the module to make it a usefull scope? 10GSps ADC as we've worked out the cost and source for you earlier? or the ADC is implemented in your project too, as odgen hinted, you have a bright future to take down some of the big names if so. we have a hope and you are our hope, good luck!


--- Quote from: ogden on January 14, 2020, 10:40:21 pm ---Year ago you...

--- End quote ---
comparing between PHP and VHDL which one is the F1 and which one is the Porche? just a side joke to release some tension.

i was just as enthusiastic, built my own FG because i dont like the taste and price of existing FG/AWG. built a crap grade Arduino Logic Analyzer, and it just went poof when i got a $10 knock off salaea LA, now with a $100 Uni-T AWG bought, i can put my diy FG at rest. i asked in forum how to deal with GSps memory pipelining, and thats it, i never continue further when thinking i maybe just wasting time and money buying wrong (expensive) parts by mistake that i have no clue about. thankfully my day and part time job have struggled enough to reward me with some old high end gears, one member are also nice enough to donate me one of them as well, so the crave for enthusiasm settled down a little bit. i still have this funny idea for GHz SA and VNA man :phew: there are more to tell about the dream but i dont feel like typing it all, i may just wasting my time here, simply short... it was the time.. i should concentrate on building my dream printer or CNC machine, because they are 5 digit price (with proper spec) and there is very slim hope that someone will come up with cheap knocked down alternative. or maybe i just keep working hard and just buy them off the shelf when i have enough money :-// we always trade time with money but if i have money i will save time. yeah, sometime its chicken and egg problem. <end of useless mumbling>
donotdespisethesnake:
Might be worth mentioning https://chips4makers.io/ at this point.


--- Quote --- The Chips4Makers wants to make it possible for makers and hobbyists to make their own open source chips.

Chips4Makers Beta

Currently the Retro-uC pilot project is being developed and being planned to be taped-out mid next year. Together with that design also some first customer chips could be produced.

If you have an open source digital (FPGA) design and envision turning it into your own chip, you may contact us. The program is currently under beta meaning that the toolchain is under heavy development and help and support from your side may be needed to get it up to shape for your design. Also the tape-out date is not known yet and no guarantees can be given that your design will be on that tape-out. Also due to the use of mature process technologies there are restrictions on performance and size of the design.
A custom (analog) design can also be discussed if the designer is prepared to take the risk of non-functional silicon.
--- End quote ---
ogden:

--- Quote from: donotdespisethesnake on January 14, 2020, 11:59:38 pm ---Might be worth mentioning https://chips4makers.io/ at this point.

--- End quote ---
Very good resource to learn from. They started project with good intentions in 31jan 2018 or even before that. Where are they now? - Nowhere. Still nothing, no ASIC. That is about digital ASIC which could be copy-pasted from VHDL/Verilog of FPGA if properly designed from beginning.
Navigation
Message Index
Next page
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod