Electronics > Projects, Designs, and Technical Stuff
Oscilloscope ASIC Kickstarter instead of Open scope.
Mechatrommer:
--- Quote from: blueskull on January 16, 2020, 07:13:10 am ---Modern embedded processors can easily plot 8-bit or 10-bit data on screen at 60fps, even without much intervention from the CPU. Embedded GPUs can easily do that.
10 years ago that might be a good idea, not anymore.
--- End quote ---
still a good idea or at least it should not hurt with modern FPGA. mcu not just to draw 60fps. it has to do math, USB to PC or pendrive capture, GUI, simple FFT etc. etc user interaction. look what happened to Rigol DS1000Z series. crawling slow GUI, only to stop acquisition just to get the responsiveness a bit better.
edigi:
--- Quote from: Mechatrommer on January 16, 2020, 02:17:26 pm ---simple FFT
--- End quote ---
Interesting but not very competitive idea, when nowadays even entry level DSOs can do 1M point FFT. No FFT in MCU.
While the MCU may only refresh the LCD with 60Hz only, the intensity graded waveform can contain the accumulation of several thousands of waveforms that can be done only in FPGA/ASIC.
Only one such glitch (missing requirement) in the ASIC design and either the project has to live with the gap or create a redesign for huge pile of money.
Mechatrommer:
--- Quote from: edigi on January 16, 2020, 02:35:14 pm ---
--- Quote from: Mechatrommer on January 16, 2020, 02:17:26 pm ---simple FFT
--- End quote ---
Interesting but not very competitive idea, when nowadays even entry level DSOs can do 1M point FFT. No FFT in MCU.
--- End quote ---
well you know, when everybody only care about $5 cheaper DSO... (less one chip) but if FFT can be fitted in the FPGA at $0 cost, why not? (but istr dso with dedicated 1Mpts FFT IC is not $5 cheaper)
ogden:
--- Quote from: OwO on January 16, 2020, 02:13:58 pm ---The FPGA/ASIC doesn't/shouldn't draw the actual image displayed on the screen. It "plots" traces by taking group min/max, for example min/max for samples 0-1023, 1024-2047, 2048-3071, etc.
--- End quote ---
Yes, software/CPU itself may take raster image prepared by FPGA, put it on the screen @60fps together with other stuff like grid, axis and additional info. What I am telling that CPU can't handle each of "0-1023, 1024-2047, 2048-3071" traces because they can come at 60000 times per second even on lo-end scopes such as Rigol DS1xxx series. Better scopes have even faster waveform processing & update speed.
ogden:
Long time no see. Any progress? Where do we line-up for scope ASICs?
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