thank you johanen, thats an answer. so you prefer method 2, and suggesting the display mechanism should be through FPGA...
i maybe got it entirely wrong with that. i'm not a PRO, i'll probably got messed up. so i've made a new sketch based on your recommendation.
"if your trying to match a rigol your looking at 1 GS/s thats a 1 GHz ADC "
if i want that, i could sketch 2x5 ADC and discuss more on how the interleaving/staggering clocking mechanism works as Mr Dave proposed earlier in his video.
"If you are doing this for a learning exercise then great, go for it"
thank you sir, i'm in the process of learning.
"You are forgetting that the most difficult part of an oscilloscope design is actually the analog front end. It's nowhere near as easy as just the "ADC" block you show."
since everybody suggesting, that this is an impossible beast to tackle. then let me give a scenario. Let say i have a project team, we want to build a complex DSO... so we have to split the tasks. one guy will be doing analog (which is where he good at), one guy will be doing digital, and another guy is doing the software/firmware. So it happen, i got stucked with designing digital side of the hardware. so i have to settle my own part.
And another intention, is to get more idea on how this FPGA/MCU/ADC/RAM/EEPROM get together to work, or simply how a FPGA works? as johanen has suggested, that the FPGA is more appropriate to handle the display mechanism. And how the actual (analog) data, got feed up into the (digital) processing and display. But i'm not going in depth into that, i know somehow, it is going to be complex either, i just want a general idea
Me? designing analog? sorry to say, hell no! my knowledge got nowhere near it! not because i dont want to.