Over voltage protection design question

[skysurf76]

I am designing a replacement for an old part.  The old part had to pass a safe to turn on resistance test of 8-40 ohms.  The new design has input power handled by an LDO that by itself would read ~3 megaohms to a DMM.  The LDO I selected can handle 60 volts input.  The expected input power is 5 volts.  I selected the LDO because I wanted to make the new design fault tolerant.  Some time after I selected the LDO I discovered the fact that the input must measure between 8-40 ohms.  I have tried everything I can think of to provide a 30 ohms measured resistance on the input while maintaining the 60 volt fault tolerance without success.  In essence I need a device in parallel with the LDO that will show 30 ohms resistance to a DMM, but that will go open circuit with any input voltage over 3 volts (the maximum voltage DMM will produce in this range of resistance).

Right now the only solution I have is putting a 2 watt resistor in parallel with the LDO so the safe to turn on test passes.  That resistor will continuously dissipate a little less than a watt and can only handle up to 7.7 volts input.  I would love to find a solution where the DMM read between 8-40 ohms, but when 5 volts was applied to the input the path through the 30 ohms resistor was turned off.

I should also mention that I am extremely space constrained on the board.

Any ideas would be massively appreciated.

I also asked many people why there was an upper resistance limit on a safe to turn on test, and no one had any answers.

[thm_w]

Some time after I selected the LDO I discovered the fact that the input must measure between 8-40 ohms.

This doesn't make sense as a requirement. First step is to find out why someone wants it done this way. Or if it is part of a regulation.

You could probably have a zener/voltage divider going to a depletion mode FET, which shuts off the resistors when 5V is received. Or maybe a low current PTC. But this is a waste of time to design blindly.

[Someone]

Some time after I selected the LDO I discovered the fact that the input must measure between 8-40 ohms.

This doesn't make sense as a requirement. First step is to find out why someone wants it done this way. Or if it is part of a regulation.

Millitary or Railway procedures have this sort of requirement so that a non-skilled person can do basic validation of the system when working on it. When those systems are in place for decades it ends up with bizarre situations like this.

[ajb]

If >5V is a fault, then you could protect the resistor and the device as a whole with a TVS+fuse/polyswitch rather than trying to design something that will just sit there and take 60V.

A depletion mode FET could be the basis of a solution to disconnect the resistor, but the trick is pulling the gate negative to turn it off when the device powers up. Just putting it between the top of the resistor and pulling the gate towards ground won't work because the source also gets pulled to ground as the FET turns off, and you end up with a current source (or you flip it around and the body diode will be forward biased which is also a problem).

A relay could work, but obviously at the expense of board space.