EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: sadboi on December 08, 2023, 04:52:08 am
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Hi,
I am trying to use p-channel JFET as a switch that is normally closed when the circuit is unpowered.
I'm simulating the the SST177 (datasheet here) (https://www.linearsystems.com/_files/ugd/7e8069_0f4d0aa8f4e8406d999bc4cdaa14aa1a.pdf) in LTSpice, which has Id=10nA when Vgs(off)=2.25V. I am seeing the circuit conduct when Vgs=0, however when the voltage increases to above 2.25V it still conducts significant current.
Is the simulation model wrong or am I completely wrong about how JFETs work? I've attached the spice circuit and plots.
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From this video:
WORKING OF P CHANNEL JFET | SEMICONDUCTOR DEVICES | PART NO 34
https://youtu.be/gpRKP907VpM
V_GS is positive and the drain-source voltage is usually negative - i.e. the source is more positive than the drain. This would mean reversing V5 in your schematic.
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The JFETs are symmetric and drain and source are exchangable. The one with the more positive voltage gets to function of source. So the FET is not working in a source circuit as a kind of switch, but more like a source follower.
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In short, the gate has to be (sufficiently) reverse biased with respect to both remaining terminals to really stop conduction.
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V6 needs to exceed V5 by 2.5V, so 8.5V, to switch J2 off.