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Package Choice

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David Hess:
DIP or PLCC (plastic *leaded* chip carrier with the j-leads) would be my first choices.  After that, I would go with the surface mount package which has the largest leads.  The old ceramic LLC would be good also but always must use a socket which probably is not a problem.

radix:
Do you have access to a wire bonder? In development, we often bond the die to an adapter PCB that can be of any size and shape. Not sure about the mechanical requirements for such a big die, though.
If the devices are to be used or sold, you can instead think about wafer probing them before packaging.

jmelson:

--- Quote from: kbarnette on March 05, 2019, 03:23:55 am ---Hello!  I'm working on a test rig for a senior design project that will take a newly fabbed and packaged chip and run some tests on the different devices in the package.  An "incidental" decision the semiconductor fabrication team has also asked me to decide is what package to use when they're done with the die fabrication.  This isn't for high volume production, nor is it speed critical.  The preference is for 48 pins but somewhere between 24 and 48 would suffice.  The main constraints will be ease-of-packaging and the ability to find a ZIF socket into which we can insert many of these devices packaged in the chosen format for testing.  Here's the kicker, the smallest size of the die they're manufacturing they can get to is 18.75mm x 18.75mm.  They've recommended Kyocera as the package manufacturer they'd like to stick with.

Am I correct in my finding that this is quite a large die?  Does anyone have any suggestions on where to find a package that will fit the constraints above and for which it will be easy to find and use a ZIF socket?

--- End quote ---
Yes, 18.75 mm square is a HUGE die!  This is going to cost a HUGE amount at any fab.  Have they checked this out?  I'm thinking a run of 40 of these would cost about $100K at MOSIS in any of their processes.  We have a quite sophisticated 16-channel mixed-signal chip in 300 nm process and it is only 6 x 9 mm or so.  We currently package it in a 128-pin TQFP package.

You will NOT find any small pin-count packages that can handle such a huge chip.

Ironwood makes fancy test sockets for custom ICs, but they are pretty expensive.  We paid about $750 each for our 128-pin TQFP test sockets.

Jon

jmelson:

--- Quote from: kbarnette on March 05, 2019, 04:09:27 am ---The die is so big because it's being manufactured by a grad student and consists of very few but very difficult to fabricate experimental memory technologies.  There isn't a lot of logic, nor is there a large power requirement  I'm expecting less than 1mW to go through the device for short periods of time during characterization of the devices.


--- End quote ---
AH, OK, not commercially fabbed.  Well, you can get open-cavity ceramic PGA packages through MOSIS or wherever they get them from, that will hold this big a die.  You can probably get one that is compatible with some old Pentium PGA CPUs, and buy ZIF sockets for those from the usual suppliers or surplus.

Jon

kbarnette:
I got some clarification that the previous measurements were the template for fabrication and the actual dies will be 2mm x 2mm, which is more in-line with what I'm finding for a die cavity size in standard packages.  I learned a lot from your responses!  Thank you all!

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