Pass Transistor Driver Problems

[ZeTeX]

Hi,

I'm designing a psu and I'm having problems with my pass transistors driver.
the problem is that if I for example set the current to be limited to 3A, it does limit to 3A, but when I change to load to higher resistence that is less then the set current (for example 10mA load while the current is limited to 3A) the output voltage is higher then set.

It does regulate the voltage correctly for set currents less then 1A, but for anything 1A the output voltage is not what I set.

Schematic here:

[TLengr]

Hello there,

Did you design this regulator circuit yourself? One possible answer is that the series pass transistors may not be operating in their linear region with load current above 1A. You might want to measure the series pass C-E voltage while varying the load current. What is the expected output voltage and at which point does it appear? I think maintaining voltage regulation over a 0.01A - 3A (300:1) range is probably asking a lot of any regulator. However, at low load currents, it looks like U3/Q3 should provide some shunt loading to help hold the output voltage down. Hope this helps.

Regards

[mij59]

The output voltage is reference to Q2, the voltage_set is reference to ground, therefore the voltage drop across R3 is  subtracted from the output voltage.

[ZeTeX]

The output voltage is reference to Q2, the voltage_set is reference to ground, therefore the voltage drop across R3 is  subtracted from the output voltage.

I think I fixed it, I'm trying to use summing amplifier that will take the set voltage + the voltage drop across the sense resistor, and add them together - so voltage set = voltage output.
now it seems like it fixed.. but I'm still playing with it.

[TLengr]

"I think I fixed it ..."

Congratulations! If I may offer a word of caution; be careful, you have not modeled a source impedance for V3. In your SPICE model this allows the collector voltage of the series pass to remain constant which is usually not the case in the "real world". Good luck.

[mij59]

The output voltage is reference to Q2, the voltage_set is reference to ground, therefore the voltage drop across R3 is  subtracted from the output voltage.

I think I fixed it, I'm trying to use summing amplifier that will take the set voltage + the voltage drop across the sense resistor, and add them together - so voltage set = voltage output.
now it seems like it fixed.. but I'm still playing with it.

Or disconnect the ground from V3 and R3, connect the ground to Q2 and connect the lead from R3 to the negative terminal of V3, and use a inverting current sense amplifier.

[ZeTeX]

The output voltage is reference to Q2, the voltage_set is reference to ground, therefore the voltage drop across R3 is  subtracted from the output voltage.

I think I fixed it, I'm trying to use summing amplifier that will take the set voltage + the voltage drop across the sense resistor, and add them together - so voltage set = voltage output.
now it seems like it fixed.. but I'm still playing with it.

Or disconnect the ground from V3 and R3, connect the ground to Q2 and connect the lead from R3 to the negative terminal of V3, and use a inverting current sense amplifier.

Doesnt work, the loop osciliates..
what have I done wrong?

[Kleinstein]

I would expect the down-programmer part to oscillate. There is another mistake in the part, as there is no well defined bias between the two possible outputs. So any offset in the OPs changes things a lot. So feedback for the sink circuit should  have an extra small resistor to the output and feedback from there instead of the output.

[ZeTeX]

I would expect the down-programmer part to oscillate. There is another mistake in the part, as there is no well defined bias between the two possible outputs. So any offset in the OPs changes things a lot. So feedback for the sink circuit should  have an extra small resistor to the output and feedback from there instead of the output.

Down-programmer unfourmently has nothing do with it, if I remove it completely it doesnt change anything.

[Kleinstein]

The output stage still has a lot of large power transistors but only a simple resistor providing base current. This might be rather slow and would not give much current anyway. So at least something like a Darlington configuration is needed, thus one more NPN transistor to drive all the TIP35 in parallel. Only 0.1 Ohms emitter resistors is rather low - this could also make stability difficult.

The capacitor C10 might need to be much larger or a combination of several.

The combination of output capacitors usually needs to be a a combination of low ESR capacitor and one with an ESR in the 0.1-1 Ohms range. The capacitor with some ESR (comparable with emitter resistors) might be needed. Only 1 µF is also very low - so may be difficult to get stable under all conditions, especially with slow transistors like the TIP35.


Depending on the performance of the output stage, the compensation may need adjustment. Currently there is only a single cap in feedback - this might be Ok for low capacitive load, but could be a problem for higher capacitance.

The capacitor directly to ground after the transistors is also not very helpful for stability.

[ZeTeX]

The output stage still has a lot of large power transistors but only a simple resistor providing base current. This might be rather slow and would not give much current anyway. So at least something like a Darlington configuration is needed, thus one more NPN transistor to drive all the TIP35 in parallel. Only 0.1 Ohms emitter resistors is rather low - this could also make stability difficult.

The capacitor C10 might need to be much larger or a combination of several.

The combination of output capacitors usually needs to be a a combination of low ESR capacitor and one with an ESR in the 0.1-1 Ohms range. The capacitor with some ESR (comparable with emitter resistors) might be needed. Only 1 µF is also very low - so may be difficult to get stable under all conditions, especially with slow transistors like the TIP35.


Depending on the performance of the output stage, the compensation may need adjustment. Currently there is only a single cap in feedback - this might be Ok for low capacitive load, but could be a problem for higher capacitance.

The capacitor directly to ground after the transistors is also not very helpful for stability.

Thanks for your suggestions, really helping me alot.
After all of your suggestion the loop still osciliates.
here is a picture of the osciliation, blue waveform is the voltage at V5, green waveform is the curent across R9.


And here is the schematic now:

[TLengr]

I think the next thing is to re-establish a ground return for source V3. As drawn, V3- is floating. One could ground “O2” and remove the connection of R29 from O2 and move it to the junction of R3 and V3-. Regards.

[amspire]

The oscillations are almost 100% guaranteed in the initial stages of a power supply design like this.

Ideally, the opamp has a 90 degree phase shift, you have a Darlington pass stage that often adds significant phase shift, R2 will add a little phase shift, R12/C7 adds a bit, and the 22uF on the output is adding significant phase shift.  You can almost bet on getting 180 degrees total phase shift somewhere and ending up with an oscillator.

You are at the point you want to start to use LTSpice to look at loop gain/phase plots. There is a great tutorial here:

Code: [Select]

https://www.youtube.com/watch?v=YYWlPFBebfc

The two key concepts are (1) that by adding a voltage source set to 0V DC into the loop, you can use it to inject a signal for AC analysis, and by plotting the ratio of this injected AC to the output AC, you get the open loop response. Concept (2) is that you can use the STEP option to run the curve with multiple component values or multiple loads together, so you can easily see the effect of any changes.

Make sure you try different loads - particularly capacitive with different ESRs. Don't get too worried about some instability with a 10,000uf capacitor with no ESR - most supplies are not fully stable for every load, and instability with a huge capacitance is not too serious as the big capacitance is flattening the voltage anyway. In fact, I would add an extra resistor to simulate the ESR of the 22uF capacitor as it does affect the phase margin with low loads and resistive loads.

Pay particular attention at the phase shift at the 0dB loop gain point with the different loads.

Once you get the hang of analysing loop gain, you will find you can analyse the gain and phase shifts of individual sections - like the Darlington stage. Adding a resistor from the emitter of Q4 to the junction point of all the 1 ohm emitter resistors will make the current in Q2/Q4 more constant over the different loads and may make their behaviour more predictable as far as AC analysis goes.

Once you get the voltage loop right, you have to do it again for the current limit loop.

[ZeTeX]

I think the next thing is to re-establish a ground return for source V3. As drawn, V3- is floating. One could ground “O2” and remove the connection of R29 from O2 and move it to the junction of R3 and V3-. Regards.

And then where would the opamp non inverting input would go? because if it will stay ground, the op amp inputs would be shorted, if I change the non inverting input to the negative terminal of V3, it doesnt work (the current doesnt regulate, the voltage is kinda weird but regulates.

amspire - thanks your very much for helping, I will come back later and watch, hopefully I could understand all of this.

[T3sl4co1l]

Gah, why are you people always recreating this circuit, and why is it always so bad?  Is there really truly no reference design out there to start from?

The "30V, 3A power supply" must be the most abused circuit in the history of this forum.

Tim

[amspire]

Gah, why are you people always recreating this circuit, and why is it always so bad?  Is there really truly no reference design out there to start from?

There are reasons. First, everyone needs a power supply, so it is usually the first major learning project people tackle.

Also every power supply design is imperfect in some way - stability, transient behaviour, drift, noise. If you look at any of the HP supply ranges where they make a 15V model, a 30V model, a 60V model and a 100V model, all use the same basic circuit, but everyone has a fair number of different parts. The compensation parts are all different. The nature of power supplies is that you change a few things and you have to re-optimise the design.

If someone can design a single power supply design that is easy to customise, is not over complicated, is not expensive, does not require a specific transformer made from unobtainium, never fails, can work with other supplies in parallel or tracking mode and does absolutely everything almost perfectly would be great. Please, I want to see this circuit!

Richard

[T3sl4co1l]

I'd love to design one, but there's no incentive to do so...

And who cares about HP anything: the only people who are interested in making/buying these things are cheap, or beginners, for which one of those shitty nameless Chinese units is fine*.

So I'm left yelling at the screen whenever these things pop up...

(*Fine in the sense of, "it'll blow up on you after a few weeks/months of use, but it was only $30, so who cares.")

Tim

[Kevin.D]

Zetex :- As you have it at the moment You have left V3 floating .You have to put a GND connection at top of R3 (O2). Then invert U4 connections ( so leave noninv to GND as it is , then connect R4 to low side of R3) .

Regards

[Kleinstein]

The circuit is trying to work with a kind of integral regulator only - this seldom works.

The first step would be to test an optimize the output stage alone, usually there is a resistor bypassing the base emter junction of the final transistors. This helps to turn of the transistors a little faster and improves operation at low output currents. For protection there usually needs to be a kind of diode to prevent the base of the Darlingtion to go to negative - as a consequence the current through the PNP also needs some current limiting. This looks like small details, but its better to have them there from the start, not to get surprised later from possible negative effects.

For later stability the output current into a high capacity  load as a function of input voltage is important. This should give a relatively fast (high) frequency response and not too much phase shifts (preferably less than 90 deg. for most of the range).

A second point for the output stage it too look at the output impedance of the transistor stage and the output caps alone. In the simulation a current source (as a spice element) as a load is very handy. This combination should be well behaved (e.g. less than 90 deg. phase shift - so representing a passive circuit). In this step the output caps, especially the damping part may need adjustment. So you see if you need 100 µF or can get away with 1 µF and suitable ESR of output capacitance for stability. Later one might want to add more low ESR capacitance to get better regulation / pulse response.

The third step is than to match the voltage control loop to the output stage. This usually needs at least a proportional and integral term, that is a resistor in series with C4.  One might also need a kind of phase boost across R8 to get a really fast response, but it should also work without. One way to to this is by looking at the AC output impedance with feedback. Here again like in the step before the phase shift must be less than 90 degree at all frequencies.
Usually one needs to start with little feedback to start from a stable point and than adjust the compensation so that more feedback is possible.  As an addition degree of freedom one could also add additional output capacitance in parallel to the one from the step before. Usually one get an output impedance to start of very low at DC or low frequencies than increase about proportional to frequency than has a maximum somewhere in the 10-1000 kHz region and than fall down to the ESR of the output capacitor. Something like a peak output capacitance of about 1-10 Ohms at 100 kHz would be a reasonable value.

The final test is the pulse response, especially with pulses down to rather low currents (e.g. 1 A to 10 mA) and different extra output capacitance. Even if the simulation is stable in the small signal regime of AC simulation, the pulse response could show trouble and may require to adjust the output stage and start over.  If you are lucky just add enough low ESR ouput capacitance to get good pulse response.

Adjusting the current regulation is similar but usually not that critical. The cross over between CC and CV mode may still be tricky, to avoid overshoot here.

[ZeTeX]

I would expect the down-programmer part to oscillate. There is another mistake in the part, as there is no well defined bias between the two possible outputs. So any offset in the OPs changes things a lot. So feedback for the sink circuit should  have an extra small resistor to the output and feedback from there instead of the output.

Alright, I finally got it working but then as you said the down programmer started to osciliate because of the offset between the comprator inputs.
" have an extra small resistor to the output and feedback from there instead of the output."
so you are suggesting resistor from O1 (output) and then take the feedback for the comporator from there?
if yes, then how would that work? what would the resistor do?

[diyaudio]

Gah, why are you people always recreating this circuit, and why is it always so bad?  Is there really truly no reference design out there to start from?

The "30V, 3A power supply" must be the most abused circuit in the history of this forum.

Tim

I agree with Tim on that.

If you really want to build a functional working circuit why not use a proven reference design ? like the e3610a ? instead you at the mercy of guesstimation.
http://sites.fas.harvard.edu/~phys191r/Bench_Notes/A1/agilent_e3610a.pdf

[ZeTeX]

I've made some changes with the driver and some small things, but I have this weird problem where the output current would not limit to 3A (while the voltage is set to 25V and the current to 3A) with 8.1ohm load connected, what happens is that the current just stays at 532mA. the resistor should try to draw 3.086A.
I cant figure out why it keeps happeing.
Schematic:

[Kleinstein]

A problem could the limited base drive current. The TIP31 don't have a very high amplification, and the 100 Ohms in series limits the current at higher output current. One might need a 3 rd transistor, one with higher gain for the first stage or a slightly lower resistance at the OP.

The supply of the driving OP might limit the output voltage anyway to something like 5 V lower than it's supply.

Such problems are usually easy to spot in the simulation. It's one reason to do the simulation. Though the more important purpose of the simulation is to check stability.

[ZeTeX]

A problem could the limited base drive current. The TIP31 don't have a very high amplification, and the 100 Ohms in series limits the current at higher output current. One might need a 3 rd transistor, one with higher gain for the first stage or a slightly lower resistance at the OP.

The supply of the driving OP might limit the output voltage anyway to something like 5 V lower than it's supply.

Such problems are usually easy to spot in the simulation. It's one reason to do the simulation. Though the more important purpose of the simulation is to check stability.

Unfortunately its not the base drive current, I've changed the transistors to FZT849, Tried reducuing R6 to lower resistence, tried replacing the op amp with LT1886 (http://www.linear.com/product/LT1886) and still the same issue.

[Kleinstein]

My guess would be the diodes D3 and D4 - but the simulation will show for sure.