Electronics > Projects, Designs, and Technical Stuff

PCB Layout for TPS54202 DC-DC Converter

(1/3) > >>

girishv:
[ Specified attachment is not available ]Hi,

I am designing a DC-DC converter, 24V input and 5V/2A output. I am using TI TPS54202 and using the schematic provided by TI Webench Power Designer.

Here is the initial layout.



I have deviated the layout guidelines provided in the datasheet for the switching network. Please suggest how I can make this better?

tooki:
For starters you seem to have entirely missed a connection in the feedback (voltage setting) network. As laid out here, it won't work at all.

The input caps (C1, C2) should be as close to the chip as possible, ideally with their grounds directly tied to the GND pin of the IC. (This is why, in TI's reference designs, and Webench, the SW connection actually goes under the input cap.) So should the feedback network (R1, R2, C4). The output caps (C5-C7) should also be rotated 180 degrees so their grounds are facing towards the chip.

Study the PCB layout in Webench and the one in the eval module: https://www.ti.com/lit/ug/slvuap3a/slvuap3a.pdf as well as the layout guidance in the datasheet.

girishv:

--- Quote from: tooki on May 19, 2024, 12:09:13 pm ---For starters you seem to have entirely missed a connection in the feedback (voltage setting) network. As laid out here, it won't work at all.

The input caps (C1, C2) should be as close to the chip as possible, ideally with their grounds directly tied to the GND pin of the IC. (This is why, in TI's reference designs, and Webench, the SW connection actually goes under the input cap.) So should the feedback network (R1, R2, C4). The output caps (C5-C7) should also be rotated 180 degrees so their grounds are facing towards the chip.

Study the PCB layout in Webench and the one in the eval module: https://www.ti.com/lit/ug/slvuap3a/slvuap3a.pdf as well as the layout guidance in the datasheet.

--- End quote ---

Thank you very much for the feedback. I should have enabled the rats nest and verified all the connections. Totally stupid of me!

Further, I will work on your suggestions and redo the layout and post here.

Thanks again.

Harry_22:
Hi! Fully agree with Tooki. You have to make ripple current paths as short as possible.

Every current is a closed line. I draw two lines of ripple current. The first flows through the upper MOSFET the second through the lower.
Your goal is to make their PCB journey shorter.

I don’t understand why you installed the diode rectifier. If you supply AC voltage you need to install an electrolytic capacitor. The reason is the same to short the ripple current from AC.

T3sl4co1l:

--- Quote from: Harry_22 on May 19, 2024, 06:47:45 pm ---Hi! Fully agree with Tooki. You have to make ripple current paths as short as possible.

Every current is a closed line. I draw two lines of ripple current. The first flows through the upper MOSFET the second through the lower.

--- End quote ---

Note that the local switching loop is terminated by the bypass capacitor adjacent to the regulator.  The loop including the inductor is hardly relevant as dI/dt is small -- literally, the inductor breaks the high-frequency loop.  At the remaining (low) frequencies, the GND plane stitching and area are more than adequate for commercial EMC purposes, I would say.

There might still be feed-through due to EPR and EPC of the inductor (equivalent parallel..., in analogy to a capacitor's ESR/ESL), for which one will need the characteristics of the inductor to analyze.  It's almost certainly fine, short of an intentionally-pathological component.

The input ferrite bead might still conduct enough EMI off the input cap to be a problem, though.

Tim

Navigation

[0] Message Index

[#] Next page

There was an error while thanking
Thanking...
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod