### Author Topic: PCB power planes  (Read 30767 times)

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#### Alex Eisenhut

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##### PCB power planes
« on: February 02, 2022, 06:12:35 pm »
Assume a complex multi-layer (>10) board, with dozens of power supplies like 3.3, 1.8, 0.93V,, with several very large FPGAs and CPUs and RAM, and PCIe lanes and Gbps SFPs and Ethernet. Suppose it's just the usual 62 mil thick roughly 6 x 4 inch typical board.

Each power supply will probably have a lot of noise on it even with as many capacitors as you want, usually dependent on what the CPU is running, you'll have frequency peaks that depend on software loops and how much memory is accessed, etc.

Now suppose the inner structure of the board is mostly power and ground planes, as only three inner signal layers are required. Outer layers are signals, no HDI stuff here, no outer planes. Through hole vias.

Here's the thing. If a lot of different power planes are adjacent, like a big 3.3V on layer 3, is completely face to face with a 1.8V plane on layer 4, aren't these supplies now capacitively coupled inside the PCB with a very low inductance as well?

In other words, whatever noise voltage is on one supply, it will now be coupled by the metal to metal capacitance of the copper structure. Right?

If that's true, then pretty much anything you measure on one supply is the combination of noise of many supplies.

In this case, if I'm right, spending a lot of time trying to add decoupling capacitors or nit-picking "local ground" for switching power supplies is the wrong approach.

The noise in the board is caused by poor design choices previous to whatever power supply chip you're using. Right?

Or is placing power planes face to face not a problem? I just picture a power supply with a noise voltage caused by the di/dt generating voltages from whatever LCR properties a plane has. Then add a 20pF ideal capacitor from that plane (the plane to plane inside the PCB) to whatever plane is nearby, how can you get rid of this? Just add more and more capacitors hoping to kill the noise on one rail low enough so it doesn't couple into another rail?

Or is a power plane on layer 3 with a ground plane on layer 2 coupled only to that ground plane, by magic, and the field lines, being intelligent, won't couple to the power plane copper on layer 4 because the field lines read the schematic?

I don't understand anything anymore.
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#### T3sl4co1l

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##### Re: PCB power planes
« Reply #1 on: February 02, 2022, 06:41:14 pm »
Sure, there's coupling like that.  Is it enough to be a problem?  It's maybe a few nF.  Not much compared to the many uF of bypasses strewn about.

Maybe it's important at higher frequencies.  Frequencies where those bypasses might not be available (via + trace + component body inductance).  Is that significant enough?  Do your loads produce enough noise at say 10-100MHz that it's actually going to cause problems?  Put numbers on it.  It's possible? Sure, fine. But how much does it matter?

Say you've got a load at 1.2V 50A, and it can turn on and off in some nanoseconds.  You need a supply impedance on the order of, say <10% ripple so 120mVpp and say the load is 0-50A step in that time so Z < 0.12/50 = 2.4mΩ.  Should only take a few bypass caps to do that in terms of ESR, and the real limitation will be how much inductance gets to them; 2.4mΩ inductive reactance at 10MHz is 38pH, so you'll need more than a few in parallel (if each one is around 3nH, evidently about a hundred!).  This seems incongruous with normal practice so this is probably an overestimate.  Remember that SoCs have onboard bypass; due to bondwire and pin inductance, there's basically nothing you can do on-board that will deal with 100MHz+ and so they must add bypass on chip (inactive gates; multiple interleaved metal layers on VCORE/GND) or interposer (wide-body or LGA type caps).

The best way to quantify supply noise is to stick an SMA (or other) connector right into the board, maybe with a coupling cap to the signal pin just so you don't worry about DC offset.  This ties right into the plane [at AC], and has good shielding so affords relative immunity in the common mode.

Note that there can be good reason to couple [supply] planes together, anyway; traces crossing between power domains, will have their image currents transferred from one to the next.  This doesn't really matter, for digital signals in multilayer stackups, as far as I know; the wave (image currents in the nearby plane) curl under the edge of one, spreading out in the space against the next plane in the stack, the impedance quickly dropping with distance and therefore time.  That spread-out wave picks up on the opposite plane, so there's just a small (~10s ps?) blip where the effective height above ground is higher.  Whereas with tight coupling (say, bypass caps straddling the seam), that spreading-out can merely be short-circuited slightly (i.e. to the length of the vias+cap).

Crosstalk can also couple to neighboring traces at these points (plane crossings), but, that's even intended behavior for differential pairs, and most of what you'll be using is that, so, no problems there.  When it's not differential, the crosstalk is still limited by trace separation relative to height to nearby ground, so, on the order of 10% coupling, whereas the logic receiver thresholds are more like 30% or something (not that there's much use of ordinary 30-70% CMOS thresholds at these rates, hehe), so still not a corruption hazard -- though certainly a chance to introduce jitter, if your application requires extremely stable timing.  The other place it would matter, SSTL or whatever kinds of unbalanced things between FPGA/CPU and SDRAM, you'll have reference planes/layers specific to that (VREF), and shouldn't need too many other supplies in the area so you can afford to fill that (VREF) out broadly.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

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#### Alex Eisenhut

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##### Re: PCB power planes
« Reply #2 on: February 02, 2022, 06:56:20 pm »
Yes, that's my whole (poorly articulated) point I suppose. If it doesn't matter to have power planes coupled to each other over a large area of PCB, how the hell does a few cm square switching power supply layout have any effect on its components?

I mean putting a local ground plane under the switcher and then sweating over whether it covers one pin of its QFN package or not is completely bonkers if several square inches of power coupling inside the PCB exists? If it's negligible at several square inches, how is a .1mm by .2mm absence or presence of copper under a device pin cause a catastrophe? At low frequencies, the waves don't "see" such small structures. It'll work either way.

But in any case, this inner capacitance has much much lower inductance than any capacitor on the outside. Maybe dozens of capacitors will "win" the fight though.

It's just that if you're going to accept power plane coupling in the PCB and deal with the noise and the board still works, why would someone spend hours and days over the placement of the soft-start capacitor of a switcher with a "local ground plane"?

By putting power planes face to face, you've shown you don't really care about what goes where, how is a 10 mil trace suddenly a problem for a single component?

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#### harerod

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##### Re: PCB power planes
« Reply #3 on: February 02, 2022, 07:04:14 pm »
...
The noise in the board is caused by poor design choices previous
...
Wouldn't it be a good strategy to keep the noise out of the supply planes in the first place? I prefer to put high frequency devices on their own supply islands, which is decoupled from the plane via ferrites. Pulse power is to be provided by the bypass capacitors. The only contiguous plane would be the 0V reference, a.k.a. GND. This setup works well for simple stuff like MCU, Fast Ethernet, USB. I always feel that I use "too many EM counter measures, e.g. ferrites, cappas", but with my usual low production numbers and high accreditation costs, passing EMC in one go makes commercial sense.

Tim, any comments on this approach with the local power islands?

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#### Alex Eisenhut

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##### Re: PCB power planes
« Reply #4 on: February 02, 2022, 07:13:29 pm »
...
The noise in the board is caused by poor design choices previous
...
Wouldn't it be a good strategy to keep the noise out of the supply planes in the first place? I prefer to put high frequency devices on their own supply islands, which is decoupled from the plane via ferrites. Pulse power is to be provided by the bypass capacitors. The only contiguous plane would be the 0V reference, a.k.a. GND. This setup works well for simple stuff like MCU, Fast Ethernet, USB. I always feel that I use "too many EM counter measures, e.g. ferrites, cappas", but with my usual low production numbers and high accreditation costs, passing EMC in one go makes commercial sense.

Tim, any comments on this approach with the local power islands?

Oh sure, that's why there's "controversies", because your way works, their way works, my way works... Unless you go out of your way to spectacularly mis-place parts, like a switcher's inductor 6 inches away and all its ancillary components at the four corners of the board.

It will work anyway.

But if that's the case, wasting time to polish a layout to look like *the one that works* isn't very productive.

Here's a datasheet

I mean this layout guideline to me is quite complex and takes up space in the real world. Is this device so sensitive to the uV of noise they're trying to avoid?

The vias that connect to its local ground will need to have extra CAD properties attached so that they don't connect to the other ground planes in the PCB. Because what is the purpose of this ground island if the ground via just connects to the next ground plane anyway?

Unless electric fields are intelligent and they know our design intent. That's always possible.
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#### Someone

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##### Re: PCB power planes
« Reply #5 on: February 02, 2022, 09:38:39 pm »
Here's a datasheet

I mean this layout guideline to me is quite complex and takes up space in the real world. Is this device so sensitive to the uV of noise they're trying to avoid?
Looks fairly tight with little wasted space. You're running some bizarre argument trying to equate overlapping power planes (capacitive coupling) with ground cuts (common impedance coupling)? They are entirely different. Many application notes are very conservative (to be fair some are just plain wrong) and like rules of thumb. They are this way so an ignorant user can make it work without understanding why, people with more insight/skill can simplify/improve the design when they know what they are doing.

Have seen many real world cases where planes did need to be separated and/or cut, but knowing when/where/how to do that is the higher skill.

#### Someone

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##### Re: PCB power planes
« Reply #6 on: February 02, 2022, 09:42:13 pm »
Sure, there's coupling like that.  Is it enough to be a problem?  It's maybe a few nF.  Not much compared to the many uF of bypasses strewn about.

Maybe it's important at higher frequencies.  Frequencies where those bypasses might not be available (via + trace + component body inductance).  Is that significant enough?  Do your loads produce enough noise at say 10-100MHz that it's actually going to cause problems?  Put numbers on it.  It's possible? Sure, fine. But how much does it matter?

Say you've got a load at 1.2V 50A, and it can turn on and off in some nanoseconds.  You need a supply impedance on the order of, say <10% ripple so 120mVpp and say the load is 0-50A step in that time so Z < 0.12/50 = 2.4mΩ.  Should only take a few bypass caps to do that in terms of ESR, and the real limitation will be how much inductance gets to them; 2.4mΩ inductive reactance at 10MHz is 38pH, so you'll need more than a few in parallel (if each one is around 3nH, evidently about a hundred!).  This seems incongruous with normal practice so this is probably an overestimate.  Remember that SoCs have onboard bypass; due to bondwire and pin inductance, there's basically nothing you can do on-board that will deal with 100MHz+ and so they must add bypass on chip (inactive gates; multiple interleaved metal layers on VCORE/GND) or interposer (wide-body or LGA type caps).
As you say parasitic/physical inductance comes in pretty quickly in power distribution, neatly overlapping with the frequencies where plane capacitance effects are. So if the plane is collecting capacitively coupled noise, most of it will be promptly rejected on the way to the load.

#### T3sl4co1l

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##### Re: PCB power planes
« Reply #7 on: February 02, 2022, 09:45:18 pm »
I mean putting a local ground plane under the switcher and then sweating over whether it covers one pin of its QFN package or not is completely bonkers if several square inches of power coupling inside the PCB exists? If it's negligible at several square inches, how is a .1mm by .2mm absence or presence of copper under a device pin cause a catastrophe? At low frequencies, the waves don't "see" such small structures. It'll work either way.

Right?  We can calculate all of these things.  Indeed, we are privileged to work in one of the few domains where, in principle, everything can be known to very high exactness!  Now, actually doing a, say, full EM simulation of a PCB, even a small part of it, is not exactly trivial, and so we often get the problem everyone else has: not enough time/budget to do that.

But that's no reason to say we should disregard such strategy.  The mere existence of such proof, should give us, simultaneously: the confidence to forge ahead, knowing that we can know; and, the humility to accept that our assumptions are merely that, and that there exists stronger proof, given suitable effort.

All else is just noise, small talk between meat-computers.

So, for stuff like that, like, I always found it suspect that appnotes say things like, remove copper under the feedback node of an op-amp.  Sure it can help, but how much is it really doing, and is it inviting something much worse?  Easy sniff test: add up the area of those nodes, calculate the rough parallel-plate capacitance, then model it (simulator, if the SPICE model is available, and reasonably accurate; else spin a dumb little breadboard to test it, why not) and see if an explicit capacitor loading that node, does it have the claimed effect?  Likely it has some effect (i.e., increasing peaking, say), but it's also not the falling sky the appnotes might have you believe.  And if it is the end [of stability], you've probably got something else worse going on (using too-large resistors in the feedback divider?), so you've just discovered something about the parameter space around your intended application, not just on the exact solution but including a variance around it.  And as for hazards, opening a hole in ground, obviously, opens a window to whatever's on the other side; if that's just more ground, or a quiet supply, fine, but if it's just a 2-layer board, ehh, you're probably better off leaving it there.

For switching supplies, you rarely cut anything out, but rather, keep loops very short and compact; this might even involve islanding an inner plane for [re]use as a switch node, say; keeping the distance between components, and height between planes and components, very short.  Maybe you want to avoid capacitance to the switch node?  You certainly don't want signal traces running by there!  But removing ground around it is likely a worse idea overall.  Indeed if anything, pack more ground in around it, to reduce impedance, and if needed, return that ground locally (slotting or making an island) so it acts as a shield against lower-level grounds!

For stuff like controller grounding, PGND/AGND, possible slotting of ground pours/planes; appnote layouts are usually an okay starting point, but sometimes they make some strange calls.  For sure, pours being within some mm as shown, is almost never going to matter.  I don't know that AGND stuff really matters anyway (they never, ever document it well enough to say what difference it actually makes), and for trace lengths, bypass caps (size, proximity and number), we can guess from acceptable ripple and expected load, e.g. a controller with 1A/10ns gate drive pulses say, is dropping 0.5V peak from 5nH of stray inductance; if that's out of 12V, who cares?  Whereas, that's a half a volt we'd rather not see in a current-sense path, or feeding back to the error amp or oscillator, so route those accordingly, and, yeah, it's fine.  It can't be any better than its wire bonds anyway, don't stress yourself out trying to make it better than that.

Or most MCUs, they're fine with pretty fair supply impedance.  I'd worry more if you're doing, like, huge parallel buses -- something with external Flash/RAM and LCD (16 or 24 bit parallel) say, that's cause for concern, but just an MCU sitting there doing a little think, and chatting quietly via UART, SPI, whatever, you'd going to have a hard time breaking that even with very few bypass caps I think.  Like if it's on 4 layers, you can probably get by with one or two bypass caps for the chip.  Maybe for the whole board.  I certainly don't recommend doing a design like that from the start, but it's definitely something you can test.  (The downside, again, is time: if you aren't making these in the millions, you're hard pressed to justify spending a few $k in labor to save a few$ in capacitors on next year's production!)

Practically speaking, almost everything I do, is just common ground over planes/stitched pours anyway.  Technically speaking though, that's done with the experience of knowing where current flow paths are, and positioning components appropriately to minimize loop size; and then, if those loops are too near anything else low-level, isolation (slots) and filtering as needed.  It's unfortunately not something very easy to describe in text, nor convey without years of experience, anyway.

For my part, I've had very few SMPS layout mistakes since I started out; most of what I've seen [from others], has been some fairly glaring error, either in routing, placement, or poorly laid / cut up / completely lacking planes.  One example was a MP2456 placed by a coworker; they brought the board to me, and after a few minutes inspecting the physical board (I didn't have the design files in front of me; we did later confirm what I thought I saw), I offered the proposition: place a 1uF ceramic cap off the VIN pin of the regulator, jumpered to the nearest GND (which was either a loop over top the chip, or off to a nearby via, I forget).  Observed problem was destruction at high Vin; issue completely solved by mod.  What I observed, was a ~10mm trace from the nearest cap/plane to VIN: this chip switches pretty quickly (~10ns?) so the peak flyback voltage at turn-off was likely destroying it.  Not sure how they didn't realize how close the bypass cap should've been, but this was easily corrected (and, I hope, kept consistent in subsequent designs; I haven't reviewed any of theirs since, but also I haven't been involved in a while, so, hopefully it's been working out ).

And, appnotes.  I suspect you've been paying too much attention to them, perhaps?  Or you're working on something and finding only appnotes to read, with obvious consequences to your mental/physical health... my sympathies in either case.  They're not well written, as a whole; they must be read critically, as anything else, which, of course, doesn't help so much when you aren't in-depth with the subject matter (and if you were, why are you reading them?..), but one can still be critical within the scope of one or a few publications, looking for inconsistencies and such, without necessarily understanding the subject, or in much depth anyway.  For other things -- like, plan some experiments maybe?  Try and figure out how things work, what matters, what doesn't -- most of all, knowing how to know (and learning to learn), is a huge advantage.  For things that can't be probed (or at least very easily), like tight layouts, you might employ a comparative series of layouts with various increments of changes between them; PITA to proto (but, ever more affordable these days, as well), and still not easy to draw conclusions from (say, many interacting effects, hard to isolate the root causes/relationships), but it's still something.  Anywhere you can set up a reliable datum to work off of, is valuable; this is why RF techniques, with ground planes and well-defined ports, are so great.  It's not easy to work within, everything interacts (waves are going both directions at any given point in the circuit!), but work is possible.

I once diagnosed an offline supply that, there wasn't any grounding to speak of, the routing was Swiss cheese -- I could control EMI below about 10MHz by adding/moving EMI components in the circuit (like Y caps, etc.), but above there, it was just an absolute cacophony, noise visible at all locations, all angles, anywhere in the circuit, even some feet around the circuit!  It was literally unworkable.  The only solution I had was to re-lay the circuit, with ground planes this time.  EMI dropped by over 20dB, and EMI components were effective up to, I forget what, 60, 90 MHz, something like that.  Much more workable.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

#### T3sl4co1l

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##### Re: PCB power planes
« Reply #8 on: February 02, 2022, 10:23:11 pm »
Wouldn't it be a good strategy to keep the noise out of the supply planes in the first place? I prefer to put high frequency devices on their own supply islands, which is decoupled from the plane via ferrites. Pulse power is to be provided by the bypass capacitors. The only contiguous plane would be the 0V reference, a.k.a. GND. This setup works well for simple stuff like MCU, Fast Ethernet, USB. I always feel that I use "too many EM counter measures, e.g. ferrites, cappas", but with my usual low production numbers and high accreditation costs, passing EMC in one go makes commercial sense.

Tim, any comments on this approach with the local power islands?

Sure, a couple:
- Ferrite beads saturate, so aren't great for supply filtering.  These loads are probably light enough it's fine, though Ethernet is close (100mA+), and a powerful MCU, or one with lots of loads (so, prefer low side switching e.g. for LEDs, and MOSFET or CMOS load switches for anything else?), would likely befall that.  Anyway, easy enough to shop around for one good for the current, or use an inductor proper.
- Islanding means you disconnect the local plane from the rest of the board, and thus the value of all that extra plane capacitance.  Bypassing is more critical.
- If the supply is quiet enough anyway (or doesn't need to be very quiet), I don't have any problem filling the board with it.

Like, I don't know that Ethernet even needs a quiet AVCC or VREF or whatever; it's usually shown with a FB-isolated section for that (give or take 10/100 and 1000 being typically different output stages), but honestly I doubt it makes much if any difference in practice.  Almost no one ever does full qualifications anyway -- it's all just superstition until it's measured that one thing or another gives 101.2 versus 113.6m range on CAT5e or whatever.  And anyway, a difference like that, literally doesn't matter (exceeds the standard), but whether you're doing something that cuts it down to 99m say, or 50 or 10 -- now that's an interesting question.

- Islanding does allow you to measure local supplies, if that should be needed.  Might be good for low-power apps where you want to track things separately?

- It could be worse, in some ways.  Consider a low-jitter application between FPGAs, say: CMOS output levels, and input thresholds, are proportional to VDD, but VDDs are uncorrelated, therefore jitter is increased between the two chips.  Whereas, even if supply ripple were higher, if it's correlated between the two -- jitter may remain nominal.  (I'm not sure how this affects LVDS; perhaps the output current depends on VDD, so slew rate varies?)

- Noisy planes are bad for EMI, of course.  The board acts as a very, very thick, very very short dipole antenna, so, emitting whatever's between top/bottom planes.  We're talking ~mV to start with, so it'll have to be quite awful to be a problem for commercial EMI levels, but may be relevant for certain sensitive tests (automotive electric field?), or very stringent standards (MIL something?).  So, that'd be supply/GND for a 4-layer (no outer pours) design, and probably nothing for 8+ layers where it's easy enough to do outer grounds (i.e., Top/Bottom signal/components, Mid1/6 GND, uhh, probably Mid2/5 signals and Mid3/4 supplies then?).  And also with surface GND pours, much less important.

Have also heard about putting a guard ring around the edge of the board, top and bottom, stitched to GND.  Frankly, I'm pretty sure this is superstition, but it is a good idea specifically when multiple ground planes (particularly near the surface) are used -- this way, they aren't flapping in the breeze (with respect to each other) around the edges.  Presumably, you've got GND vias strewn randomly about the board already, leaving the edge exposed as some random combination of slot antennas or open waveguides, and this just short-circuits all those, at least up to wavelengths corresponding to via spacing.  Easy.

Same isn't the case for 4L where there's no GND-GND mode and the guard ring does nothing.  I do sometimes scatter bypass caps around the plane, for boards like this -- you'd have to use as many caps as vias to replicate it exactly, not very practical, but a few in the corners, or in blank spots where there just isn't much else going on, might help to break up standing waves between planes.

And, note that hedging language.  "Might" help.  The planes are low impedance, FR-4 is a lossy fill, it's a very low aspect waveguide environment; it's unlikely that your circuit is making much noise up there anyway (i.e. GHz; MCUs even at some 100s MHz, or even GHz, should produce very little out their leads, all the harmonics have to be handled inside the package), and due to the low cross section of the board edge, there's not much radiating field that's going to couple into or out of it.  You can measure the plane impedance with an RF connector sunk right into it; rather impractical to test literally every point on the plane in a real design, but a few spot checks can be designed in from time to time.

Or you can even set up a sort of TEM cell, as it were, with components-under-test placed upon it -- by that I mean, make a PCB as a long rectangular plane pair, with components laid out in the usual way, and C+ESR bypass stitching both ends of it (as a termination at Zo of whatever the aspect ratio gives).  Flip open one of the C+ESRs and insert a min-loss attenuator to an RF connector (or just the coupling capacitor if you don't even mind the mismatch).

Also a good environment to do the reciprocal, susceptance testing.  Or with programmed sequences of transients, intentional glitching (Chip Whisperer, etc.).  Drive it with some ripple and see if any behavior changes?

Put another way: basically, use the PCB + plane as a low-Z bias tee for supply emissions/immunity shenanigans.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

#### nctnico

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##### Re: PCB power planes
« Reply #9 on: February 03, 2022, 12:28:45 am »
Wouldn't it be a good strategy to keep the noise out of the supply planes in the first place? I prefer to put high frequency devices on their own supply islands, which is decoupled from the plane via ferrites. Pulse power is to be provided by the bypass capacitors. The only contiguous plane would be the 0V reference, a.k.a. GND. This setup works well for simple stuff like MCU, Fast Ethernet, USB. I always feel that I use "too many EM counter measures, e.g. ferrites, cappas", but with my usual low production numbers and high accreditation costs, passing EMC in one go makes commercial sense.

Tim, any comments on this approach with the local power islands?

Sure, a couple:
- Ferrite beads saturate, so aren't great for supply filtering.  These loads are probably light enough it's fine, though Ethernet is close (100mA+), and a powerful MCU, or one with lots of loads (so, prefer low side switching e.g. for LEDs, and MOSFET or CMOS load switches for anything else?), would likely befall that.  Anyway, easy enough to shop around for one good for the current, or use an inductor proper.
- Islanding means you disconnect the local plane from the rest of the board, and thus the value of all that extra plane capacitance.  Bypassing is more critical.
- If the supply is quiet enough anyway (or doesn't need to be very quiet), I don't have any problem filling the board with it.

Like, I don't know that Ethernet even needs a quiet AVCC or VREF or whatever; it's usually shown with a FB-isolated section for that (give or take 10/100 and 1000 being typically different output stages), but honestly I doubt it makes much if any difference in practice.  Almost no one ever does full qualifications anyway -- it's all just superstition until it's measured that one thing or another gives 101.2 versus 113.6m range on CAT5e or whatever.  And anyway, a difference like that, literally doesn't matter (exceeds the standard), but whether you're doing something that cuts it down to 99m say, or 50 or 10 -- now that's an interesting question.
You should also consider that anything onto those AVCC nets is going into the ethernet cable. Having a stiff (well decoupled) and filtered supply on the analog part of an ethernet phy does help a bit with passing EMC testing.

For high speed nets/hi current nets bypassing is critical anyway so I don't see islanding as bad perse. It helps to keep nasty stuff localised.

I have seen a SOC design acting up because it didn't have a bypass cap underneath the BGA. This despite the power plane itself having a ton of decoupling right next to the chip.

In another design a high speed clock distribution chip (with differential outputs) caused a lot of noise in the supply plane; a ferrite bead to isolate it (with exta local decoupling) helped a lot.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.

#### T3sl4co1l

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##### Re: PCB power planes
« Reply #10 on: February 03, 2022, 02:08:53 am »
You should also consider that anything onto those AVCC nets is going into the ethernet cable. Having a stiff (well decoupled) and filtered supply on the analog part of an ethernet phy does help a bit with passing EMC testing.

True.  Well, sort of; it depends on the driver type.  Which I'm not sure about, there's probably three kinds?  I don't know which ones are most common.  Well, I'd guess one is out, but besides that...

Anyway, for the push-pull type driver: if it's a dual NMOS type and saturating (probably just archaic 10BASE-T transmitters?), then Rds(on) pulls the winding to GND, and AVCC is applied to it, and thus the line.  That's no automatic fail, if it's noisy; you still have to go through transformer CMRR first.  But CMRR is fairly modest (typically 35-40dB) so you can fail at some point.  (Hm, which fails first, emissions or communications? Probably, emissions can fail first if it's 100BASE-T mode and the noise is all at higher frequencies (>100MHz)?)

If it's push-pull but current-sinking, then it should have good PSRR, and AVCC filtering not so important.  CMRR still matters, but a few solid bypasses and not-absolute-trash power should pass pretty much anything?  CMRR can still be degraded by Coss(Vds), which would also be a high frequency effect, maybe that could be relevant.  (The output devices should be pretty tiny, like ~10pF, not a big deal at most frequencies).

If it's H-bridge and current or voltage mode (typical of 1000BASE-T, innit?), it can be kinda either way; depends on the internal design.  It could be current-sourcing with good PSRR; it could be voltage mode, referenced to VDD/GND in all the wrong places.  Again, don't know much about 'em, alas.

Tl;dr: the balanced design and transformer isolation help a lot, but aren't a panacea.

Oh, also, CMRR is degraded for long PHY trace lengths; you want to keep the stubs short.  This is pretty easy for comms purposes (in terms of baud rate, they could be fractional meters), but performance in the 100s MHz will be more critical.

Quote
I have seen a SOC design acting up because it didn't have a bypass cap underneath the BGA. This despite the power plane itself having a ton of decoupling right next to the chip.

Hm, good to know.

Another kinda BS thing about BGAs, the via grid turns the planes into Swiss cheese -- increasing the impedance of everything and doing havoc to signal impedances.  At least there's not (usually?) much physically hanging off the chip itself (at worst a heatsink?), so the ground impedance (--> common mode) isn't a big deal, but that does get added to all the signals in/out of the chip, and of course adds to the supply impedance so that it'll be higher than expected [by a simplified model], which might well be relevant here.

Quote
In another design a high speed clock distribution chip (with differential outputs) caused a lot of noise in the supply plane; a ferrite bead to isolate it (with exta local decoupling) helped a lot.

Wow, rude!

Another case I heard of, some random National part, synchronous buck regulator, don't remember which; it was reported as producing ~ns edges, polluting pretty much the whole board with pervasive noise (making the onboard ADCs almost useless).  The waveform looked very much like body diode step recovery, occurring after the low-to-high dead time.  (What a terrible idea; you're supposed to run a sync buck with zero to negative interleave, and snub the dI/dt with supply impedance.  This gives "manually commutated" hard switching, as it were; better than the forced recovery of hard (diode) switching.  Unfortunately, very few regulators or controllers offer this, to this day.  Maybe for obvious reasons, but I still harrumph.)

Probably, that issue could've also been solved by proper islanding and filtering, assuming the free board area was available to slot around the regulator of course.  Or maybe not; low ~GHz harmonics are squirrely buggers.

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#### harerod

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##### Re: PCB power planes
« Reply #11 on: February 03, 2022, 02:44:56 pm »
Quote from: harerod on Yesterday at 20:04:14
...
Ferrite beads saturate, so aren't great for supply filtering.
...
For starters, let's just assume that the designer read the datasheet.

#### Siwastaja

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##### Re: PCB power planes
« Reply #12 on: February 03, 2022, 03:14:13 pm »
Quote from: harerod on Yesterday at 20:04:14
...
Ferrite beads saturate, so aren't great for supply filtering.
...
For starters, let's just assume that the designer read the datasheet.

Have you seen a ferrite bead datasheet that specifies saturation current? Surely they must exist, but I haven't.

Some appnotes suggest assuming that saturation current is like one fifth of the current rating or something like that, but such assumptions are risky, unless you derate it a lot for safety margin. Worse, you should know what the peak current is, but often for parts like ADCs only average is specified. Temporary saturation during the peak, when the filtering is required the most, is unexpected and worse, varies with conditions like temperature.

If you are unaware of this, you might assume that the datasheet current rating is the smaller of the two (thermal and saturation rating), but because it isn't, this is a recipe for disaster, because the gap between reality and assumption is so wide.

« Last Edit: February 03, 2022, 03:23:32 pm by Siwastaja »

#### free_electron

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##### Re: PCB power planes
« Reply #13 on: February 03, 2022, 03:23:23 pm »
Have also heard about putting a guard ring around the edge of the board, top and bottom, stitched to GND.  Frankly, I'm pretty sure this is superstition,
Nope. i've witnessed this firsthand. but there is more to this than meets the eye

The planes at the edge of the board CAN act as a dipole antenna and radiate noise
To prevent this the following buckshot approach works in 99% of the cases
- ground planes extend to board edge ( minus obligatory retract from true edge )
- power plane retract 3 via widths from ground plane edge
- stitch vias around perimeter to shunt ground planes.
- shunt RF energy by sprinkling small (1nf) capacitors at edge of board IF and WHERE a large unpopulated plane stack is present

the last statement merits some explanation.
consider a board that is sparsely populated. Let's say a VME or some other 'standard size' board that goes in a rack. The board may hold a small amount of components and be otherwise bare. The board is flooded with copper ( to save etchant)
You basically have a big dipole antenna formed between the planes. the tips (edge of the plane) will radiate that energy. Problem : these boards sit head on in a rack. so when you do a directional measurement in EMC chamber the whole front of the rack radiates like crazy.

So , retracting the power plane inwards is one way of mitigation. via stitching creates even more attenuation. shunting using a small capacitor gets even more attenuation.
yes, you could calculate and measure and figure out exactl location of the vias and capacitor value. But ... is it worth your time and or risk ? CAD tools can create such a via ring with a few mouseclicks. And it doesn't cost anything. Better safe than sorry.
Is it always necessary ? most likely not. but why risk a board / product respin ?

It needs a correct understanding why you do it. it always amuses me how today people still sprinkle 100nf capacitors everywhere for 'decoupling'. 100nf worked when clockspeeds were in the 1 to 10MHz range. drive a 100nf beyond that speed and it is an inductor.. you are past self resonance point.

other things to do :

retract soldermask off the ground planes on outer layers , especially towards the seams of the enclosure. helps with esd zaps.

Never EVER reuse self tapping screws in sheet metal that are used for grounding purposes. board in  board out , board in , board out and the EMC goes to snot ... because the screw does not make good contact anymore ! use screw clips in sheetmetal and replace the clip and screw if you repeatedly had to remove the board.

During PCB layout : any mounting hole used as a conductor needs to have a via ring. it is too easy for the screw to damage the barrel plating. The via ring provides connection even if the main hole barrel is stripped by the screw.
« Last Edit: February 03, 2022, 03:31:07 pm by free_electron »
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#### Siwastaja

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##### Re: PCB power planes
« Reply #14 on: February 03, 2022, 04:07:08 pm »
it always amuses me how today people still sprinkle 100nf capacitors everywhere for 'decoupling'. 100nf worked when clockspeeds were in the 1 to 10MHz range. drive a 100nf beyond that speed and it is an inductor.. you are past self resonance point.

Just

You know... maybe these people are right. One very successful but a bit OCD designer here who is not with us anymore, suggested using 1uF everywhere for decoupling.

At the end of the day, the circuit does not know about SRF. All that the circuit cares about, is impedance. As you can see from your plots, except for some lucky, narrow dips, the absolute impedance delivered by a 1nF, 100nF or 1uF caps at high frequency end is the same: straight line, where all the lines meet.

You talk about inductance. This is an actual physical phenomenon, and only depends on the package size and layout. 0201 1nF and 0201 100nF capacitors have the same inductance, and same absolute impedance at high frequencies. Their parallel combination performs better than 100nF alone (assuming you avoid resonances between them, so it could perform worse, too), but only because the inductances act in parallel. Paralleling 2x 100nF would work equally well, or better.

The old rule of thumb you are referring to is based on the idea that larger capacitance values always and automatically require larger packages, hence have more inductance, PCB routing difficulties included. The idea is still valid, but not usable as rule-of-thumb, because actual reality wins. Even 1uF is available in tiny 0402 or 0201 packages today. These parts filter great over a larger frequency range, than smaller capacitance, as you can see from the plot you posted. SRF is meaningless.

But yeah, if your load required lower impedance exactly at 520MHz, you could gain something by using that 100pF capacitor (violet) in that plot. But is the next 100pF cap from the next batch the same? Two of the 2.2uF caps (orange) in parallel would definitely work, giving lower inductance over the whole spectrum.

That graph is also pretty revealing how futile the work of paralleling three different capacitance values, trying to combine the impedance dips into continuously low impendace, is. Even with 5 capacitors, the coverage of lowest possible impedance is like 50%. You would need 10 different values and hope they perform the same between batches. Whereas just using the largest capacitance gives you overall low impedance, and paralleling more of the same is trivial.
« Last Edit: February 03, 2022, 04:20:54 pm by Siwastaja »

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#### harerod

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##### Re: PCB power planes
« Reply #15 on: February 03, 2022, 04:12:12 pm »
...Have you seen a ferrite bead datasheet that specifies saturation current? Surely they must exist, but I haven't....
Yes, I have. Although my original text was about "having read the datasheet". Anything containing "iron filings" usually comes with two specification, regarding current: rated current and saturation current. Their interactions are complex and differ between devices. Rule of thumb: "rated" is about self heating and may imply a some saturation. "Saturation" is about the magnetic field.

Examples, attached:
- BLM18AG121SN1 - rated current 500mA, no "saturation" info. I wouldn't have any qualms using this as a supply filter for an MCU that allows 100mA supply current. Even the mighty STM32F407 only allows 240mA total supply current. A STM32L051C8 allows 105mA. Is it the ATmega328P that is used in Arduino? This one allows 200mA total.
- LQHCxC - see Direct Current Characteristics

https://www.harerod.de/applications_eng.html#EmiFilTest
The purpose of these little boards is not to brag about may ability to drill many small holes into FR4, although I can second free_electron's post on "stitching" from decades of design and accreditation experience in medical, MIL and industrial. It works really well, but isn't necessary for all designs. On the other hand - in small scale production vias are free. Having been lied to way too often, makes me want to specify critical components. Boards like these make it easy to set up a certain filter structure and measure its behaviour. Simply DC-bias an inductor and see what happens. Insert/Remove capacitors and see how the resonant frequency changes. See how a coupe of cappas work together. Stuff like that.
As with most datasheets, the interesting information is what is missing from page one and what is missing altogether. If I want some information, I might just contact the manufacturer. They will have that data. If certain data, e.g. saturation information, is not available on request, I will most likely move on.
« Last Edit: February 03, 2022, 04:15:47 pm by harerod »

#### Siwastaja

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##### Re: PCB power planes
« Reply #16 on: February 03, 2022, 04:15:05 pm »
Examples, attached:

You are exactly proving the point - the FB datasheet does not come with saturation rating, the one sold as an "actual inductor" comes, as usual.

#### harerod

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##### Re: PCB power planes
« Reply #17 on: February 03, 2022, 04:17:54 pm »

#### free_electron

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##### Re: PCB power planes
« Reply #18 on: February 03, 2022, 04:47:49 pm »
You talk about inductance. This is an actual physical phenomenon, and only depends on the package size and layout.
correct. but ...
There is another problem. With package size also comes the working voltage problem. a 10uf x7r MLCC rated at 6.3v with 5 volt across it still has 4uf in an 0805. but snot in a 0402... body.
MLCC are susceptible to DC bias and it is heavily dependent on manufacturer.

TDK , Kemet and murata have nice simulation software

https://www.tdk-electronics.tdk.com/en/180524/design-support/design-tools
https://ec.kemet.com/design-tools/
https://www.murata.com/en-us/tool

the kemet online tool is very interesting. you can stack capacitors, apply dc bias and see what happens a  2.2uf 6v3 x7r in 0602 triples its esr and impedance (esr is not dominant and much lower than total impedance) going from 0 volt dc to 6 volt dc...

https://ksim3.kemet.com/capacitor-simulation
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#### Siwastaja

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##### Re: PCB power planes
« Reply #19 on: February 03, 2022, 05:33:42 pm »
Yes, "there can't be too much capacitance" extends up to maybe 1-4.7uF in these <5V rails. At that point, inductance starts to increase because of forced larger package (either simply due to total unavailability, or underperforming due to stronger DC bias effect), and paralleling different sizes become interesting again. At 10uF, do consider adding that 100nF in parallel again for HF.

But I was replying to the claim of 100nF (not 10uF) being inferior to 1nF. You can laugh at all those designers who do that, but yet they succeed equally. They may laugh at you. But you both have the same impedance at high frequency so pass the EMI regardless. Sure, those who try with 1000uF electrolytics soldered to the edge of the board, will fail.

The point is, it makes no sense to believe that 1nF|10nF|100nF|1uF combinations are magical. If you need 1uF for low frequencies, 4x220nF works out roughly the same (and with smaller BOM and smaller risk of resonances).

Similarly, it makes no sense to believe that 100nF everywhere is somehow inferior to hand-picking 1nF or 100pF for HF purposes, because 100nF is easily achievable in even 0201 size at which point inductance is pretty much minimized. With some luck, the 100pF part might have a slightly better dip at exactly the problem frequency, but with the opposite luck, you create a resonance. With 1uF you have minimized the impedance over widest possible spectrum. Smaller values compromise the LF, larger values force to larger package, compromising HF. SRF doesn't come into play at any point.
« Last Edit: February 03, 2022, 05:41:35 pm by Siwastaja »

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#### nctnico

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##### Re: PCB power planes
« Reply #20 on: February 03, 2022, 06:48:20 pm »
You talk about inductance. This is an actual physical phenomenon, and only depends on the package size and layout.
correct. but ...
There is another problem. With package size also comes the working voltage problem. a 10uf x7r MLCC rated at 6.3v with 5 volt across it still has 4uf in an 0805. but snot in a 0402... body.
MLCC are susceptible to DC bias and it is heavily dependent on manufacturer.
Fortunately most high speed stuff runs from 1V-ish supply voltages so DC bias is not much of an issue nowadays. Use a 10V part and you'll have 80% of the rated capacitance in even the most crappiest capacitor. So in the end: use the largest capacitance in the smallest package which still has an acceptable capacitance degradation due to DC bias that doesn't cost an arm and a leg.
« Last Edit: February 03, 2022, 06:51:10 pm by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.

#### free_electron

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##### Re: PCB power planes
« Reply #21 on: February 03, 2022, 07:28:19 pm »
The point is, it makes no sense to believe that 1nF|10nF|100nF|1uF combinations are magical.
That is indeed too much but the old small/large/bulk does work. again, in CERTAIN cases. EMI is complex and it all depends. i would not use parts that are only 1 decade apart. 1nf/100nf has a better chance . but then again you really need to look at the spectrum to decide hat you need. I was solving a problem on a drive. The thing would not pass EMC . there was too much energy in a certain range. We could not alter board layout nor price of the BOM.(when making a million of these things a day .. bom is very critical ). The noise came from a power rail.
The output used 4u7 and 22nf capacitors ( bulk and decoupling) . By switching out two of the 22nf capacitors to 150pf ( can't remember exactly but one was a 0805 , the other an 0402 i believe. it's 8 year ago... the 22nf were x7r, the pf was c0g) i was able to make enough of a dent in the spectrum so it would pass without affecting the circuit. they used 4 bulk caps and 5 or 6 of the little guys.

Sometimes you do need to tweak the PDN. network analyzers can be very helpful for that.

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#### Siwastaja

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##### Re: PCB power planes
« Reply #22 on: February 03, 2022, 07:40:25 pm »
It's also helpful that only the single representative unit is tested for EMI, and you don't have to recertify after a new batch of capacitors goes into production, or a new batch of PCBs with slightly different dielectric constant or prepreg thickness.

I refer to that violet curve on the posted example. If the EMI fails at 530MHz by a few dB, and you swap a 100n cap to this particular violet cap, you can make it pass, but the question is, is this real or just faking it, because it likely isn't reproducible.

Of course, in the reality of running a business, just getting the pass is all that matters, and the risk of getting caught from faking it is small. Even better if the designer truly believes they are doing the right thing! Bad intent is difficult to prove, anyway. By doing careful, documented adjustments, the designers have done their due diligence, clearly, even if a unit later fails EMC by 1dB in an independent control test.
« Last Edit: February 03, 2022, 07:46:56 pm by Siwastaja »

#### uer166

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##### Re: PCB power planes
« Reply #23 on: February 03, 2022, 07:47:43 pm »
It's also helpful that only the single representative unit is tested for EMI, and you don't have to recertify after a new batch of capacitors goes into production, or a new batch of PCBs with slightly different dielectric constant or prepreg thickness.

I refer to that violet curve on the posted example. If the EMI fails at 530MHz by a few dB, and you swap a 100n cap to this particular violet cap, you can make it pass, but the real question is, is this real or just faking it.

Of course, in the reality of running a business, just getting the pass is all that matters, and the risk of getting caught from faking it is small. Even better if the designer truly believes they are doing the right thing! Bad intent is difficult to prove, anyway. By doing careful, documented adjustments, the designers have done their due diligence, clearly, even if a unit later fails EMC by 1dB in an independent control test.

Even better when you pass because the test lab screwed up their equipment (janky N adapters), but still provide an official test report.

#### T3sl4co1l

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##### Re: PCB power planes
« Reply #24 on: February 03, 2022, 08:09:51 pm »
I try to avoid using anything that isn't specified.  So for example, I wouldn't use that Murata ferrite bead under more than modest DC bias.  (Or for that matter, to my knowledge, none of their beads have bias characteristics.)  Fine for logic or analog signal inputs, outputs even (say to 10 or 20mA).  But I don't know if it saturates at 50mA or 500, so it's not very useful to me as a power filter component.

The one manufacturer that reliably has bias characteristics is Laird.  The nearest substitute for that part is probably LI0603G121R-10,
https://www.mouser.com/datasheet/2/987/Laird_10092020_Laird_MCP_Catalog_EMI_Filtering_and-1947796.pdf
which shows Z(F) for 0, 100, 200, 300, 500, 700 mA.  The 100mA curve is near full (~92%), so that's promising; the 200mA curve is quite a bit lower (~50%) so should probably be considered saturated.  Mind, not to say it's suddenly useless, either -- the remaining impedance might still be enough, maybe you just need to take the edge off, whether in the meaning of a modest attenuation (10dB here or there?), or edge as in high frequencies/harmonics (100s MHz).  Zpk remains >140Ω across the series, just pushed to increasing frequencies (from about 400 to 900MHz over the series).  Maybe you just need some tens of ohms up there, so the peak wandering around doesn't really matter to you.

Note that the 20 ohms remaining at 100MHz, 700mA suggests L ~ 32nH, still significantly more than an equivalent length of wire; it's still doing something, even if not nearly as much as at zero bias (more like 300nH at 0mA, 10MHz).

Flipping through the plots, it looks like most have a similar response, varying somewhat in current (almost all 0603s rolling off (-30%) in the 50-300mA range), and the scales being weird sometimes (like the HZ0603B471R-10 showing a suspiciously tight grouping up to 200mA, or the HZ0603A252R-10 showing a most likely erroneous labeling up to "0.05 mA").  Most of the high-Z parts (1kΩ+) are much more sensitive, while the low-Z parts are, not really that much more current than the others, actually, though they also only go down to 30Ω in this catalog; such are available from other manufacturers, and may offer higher saturation currents.  (A recent thread showed off a Wurth example: https://www.we-online.com/katalog/datasheet/7427922808.pdf Also an 0603, it's a mere ~15nH, but good for a couple amperes(!).)

So, to the extent that we can infer the properties of Murata's, or say Taiyo Yuden's, or anyone else's, these data might be an acceptable starting point for anyone; but it's shaky design to do that.  Probably okay, but you never know, right.

On the upside, it's harder to cheat a ferrite bead, I think?  The body is some manner of ferrite, and the winding may be some number of turns (on a lengthwise or cross axis), or at worst, one turn straight through the middle.  I wouldn't expect saturation to be dramatically worse, or better, between comparable parts.  (A notable exception is multilayer inductors, which are constructed identically, but with a lower permeability grade of ferrite, effectively doing what powdered iron does (distributed air gap).  At least I'm assuming that's how they get the useful Q and saturation current; it's not like there's much room for a lumped air gap in there!)

Whereas ceramic caps, who knows how many electrodes they put in there, and at what spacing -- a smaller value in a given size, might simply be the same layer spacing (say comparing 0603 50V, 1nF vs. 10nF), so will have identical C(V)/C(0) curves; or they might be spaced out so it's actually an e.g. 200V cap as such, but they still sell it as 50V because, why not (probably easier/faster/cheaper to test just to the lower voltage?).  Values large enough that they require a thicker chip, are likely filling up the chip as such, but it's still no guarantee that you get a nice wide C(V) curve, especially at higher voltages.  (And for those, it seems like every X7R >100V I've seen, has embarrassingly little C left near rating -- enough that C0G are tempting, if not for the cost of large values, unfortunately.  So, film tends to be the preferred choice for large values at modest voltages.)

C0G by the way, is excellent at high voltage.  The energy density is higher than electrolytics even, though again, you'll be paying quite a lot to get the privilege of that much energy storage.  Which, if you're willing to pay that much -- there are also boutique-ish poled ceramics, that saturate just like any other type 2 dielectric, but the "zero bias" point has been shifted (by a frozen-in electric field) to a useful offset, so they have tremendous energy storage around e.g. 300-500V and almost no value near 0V.

BTW, note that ferrite beads have substantial capacitance, compared to their dimensions, and it doesn't vary with bias.  (Well, maybe it varies with applied DCV, hah, good luck testing that. )  Ferrite has a fairly high dielectric constant (like 10 or so).  So you get a zero in your filter at high frequencies (GHz+).  One way around this is to use several in series, of different value (much as it's suggested to use ceramic caps in parallel, and subject to the same limitations: check impedance carefully, make sure they don't resonate together!).

I've written a few simulation models including nonlinear behavior; play around if you like:
https://seventransistorlabs.com/Modeling/SPICE/HI0603P600R_NL.ckt  https://seventransistorlabs.com/Modeling/Images/HI0603P600R_Overlay.jpg
https://seventransistorlabs.com/Modeling/SPICE/MI1206L391R_NL.ckt  https://seventransistorlabs.com/Modeling/Images/MI1206L391R_Overlay.jpg

Tim
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Electronic design, from concept to prototype.
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