I mean putting a local ground plane under the switcher and then sweating over whether it covers one pin of its QFN package or not is completely bonkers if several square inches of power coupling inside the PCB exists? If it's negligible at several square inches, how is a .1mm by .2mm absence or presence of copper under a device pin cause a catastrophe? At low frequencies, the waves don't "see" such small structures. It'll work either way.
Right? We can calculate all of these things. Indeed, we are privileged to work in one of the few domains where, in principle, everything can be known to very high exactness! Now, actually doing a, say, full EM simulation of a PCB, even a small part of it, is not exactly trivial, and so we often get the problem everyone else has: not enough time/budget to do that.
But that's no reason to say we should disregard such strategy. The mere existence of such proof, should give us, simultaneously: the confidence to forge ahead, knowing that we can know; and, the humility to accept that our assumptions are merely that, and that there exists stronger proof, given suitable effort.
All else is just noise, small talk between meat-computers.
So, for stuff like that, like, I always found it suspect that appnotes say things like, remove copper under the feedback node of an op-amp. Sure it can help, but how much is it really doing, and is it inviting something much worse? Easy sniff test: add up the area of those nodes, calculate the rough parallel-plate capacitance, then model it (simulator, if the SPICE model is available, and reasonably accurate; else spin a dumb little breadboard to test it, why not) and see if an explicit capacitor loading that node, does it have the claimed effect? Likely it has some effect (i.e., increasing peaking, say), but it's also not the falling sky the appnotes might have you believe. And if it is the end [of stability], you've probably got something else worse going on (using too-large resistors in the feedback divider?), so you've just discovered something about the parameter space around your intended application, not just on the exact solution but including a variance around it. And as for hazards, opening a hole in ground, obviously, opens a window to whatever's on the other side; if that's just more ground, or a quiet supply, fine, but if it's just a 2-layer board, ehh, you're probably better off leaving it there.
For switching supplies, you rarely cut anything out, but rather, keep loops very short and compact; this might even involve islanding an inner plane for [re]use as a switch node, say; keeping the distance between components, and height between planes and components, very short. Maybe you want to avoid capacitance to the switch node? You certainly don't want signal traces running by there! But removing ground around it is likely a worse idea overall. Indeed if anything, pack more ground in around it, to reduce impedance, and if needed, return that ground locally (slotting or making an island) so it acts as a shield against lower-level grounds!
For stuff like controller grounding, PGND/AGND, possible slotting of ground pours/planes; appnote layouts are usually an okay starting point, but sometimes they make some strange calls. For sure, pours being within some mm as shown, is almost never going to matter. I don't know that AGND stuff really matters anyway (they never, ever document it well enough to say what difference it actually makes), and for trace lengths, bypass caps (size, proximity and number), we can guess from acceptable ripple and expected load, e.g. a controller with 1A/10ns gate drive pulses say, is dropping 0.5V peak from 5nH of stray inductance; if that's out of 12V, who cares? Whereas, that's a half a volt we'd rather not see in a current-sense path, or feeding back to the error amp or oscillator, so route those accordingly, and, yeah, it's fine. It can't be any better than its wire bonds anyway, don't stress yourself out trying to make it better than that.
Or most MCUs, they're fine with pretty fair supply impedance. I'd worry more if you're doing, like, huge parallel buses -- something with external Flash/RAM and LCD (16 or 24 bit parallel) say, that's cause for concern, but just an MCU sitting there doing a little think, and chatting quietly via UART, SPI, whatever, you'd going to have a hard time breaking that even with very few bypass caps I think. Like if it's on 4 layers, you can probably get by with one or two bypass caps for the chip. Maybe for the whole board. I certainly don't recommend doing a design like that from the start, but it's definitely something you can test. (The downside, again, is time: if you aren't making these in the millions, you're hard pressed to justify spending a few $k in labor to save a few $ in capacitors on next year's production!)
Practically speaking, almost everything I do, is just common ground over planes/stitched pours anyway. Technically speaking though, that's done with the experience of knowing where current flow paths are, and positioning components appropriately to minimize loop size; and then, if those loops are too near anything else low-level, isolation (slots) and filtering as needed. It's unfortunately not something very easy to describe in text, nor convey without years of experience, anyway.
For my part, I've had very few SMPS layout mistakes since I started out; most of what I've seen [from others], has been some fairly glaring error, either in routing, placement, or poorly laid / cut up / completely lacking planes. One example was a MP2456 placed by a coworker; they brought the board to me, and after a few minutes inspecting the physical board (I didn't have the design files in front of me; we did later confirm what I thought I saw), I offered the proposition: place a 1uF ceramic cap off the VIN pin of the regulator, jumpered to the nearest GND (which was either a loop over top the chip, or off to a nearby via, I forget). Observed problem was destruction at high Vin; issue completely solved by mod. What I observed, was a ~10mm trace from the nearest cap/plane to VIN: this chip switches pretty quickly (~10ns?) so the peak flyback voltage at turn-off was likely destroying it. Not sure how they didn't realize how close the bypass cap should've been, but this was easily corrected (and, I hope, kept consistent in subsequent designs; I haven't reviewed any of theirs since, but also I haven't been involved in a while, so, hopefully it's been working out
).
And, appnotes. I suspect you've been paying too much attention to them, perhaps? Or you're working on something and finding only appnotes to read, with obvious consequences to your mental/physical health... my sympathies in either case. They're not well written, as a whole; they must be read critically, as anything else, which, of course, doesn't help so much when you aren't in-depth with the subject matter (and if you were, why are you reading them?..), but one can still be critical within the scope of one or a few publications, looking for inconsistencies and such, without necessarily understanding the subject, or in much depth anyway. For other things -- like, plan some experiments maybe? Try and figure out how things work, what matters, what doesn't -- most of all, knowing how to know (and learning to learn), is a huge advantage. For things that can't be probed (or at least very easily), like tight layouts, you might employ a comparative series of layouts with various increments of changes between them; PITA to proto (but, ever more affordable these days, as well), and still not easy to draw conclusions from (say, many interacting effects, hard to isolate the root causes/relationships), but it's still something. Anywhere you can set up a reliable datum to work off of, is valuable; this is why RF techniques, with ground planes and well-defined ports, are so great. It's not easy to work within, everything interacts (waves are going both directions at any given point in the circuit!), but work is
possible.
I once diagnosed an offline supply that, there wasn't any grounding to speak of, the routing was Swiss cheese -- I could control EMI below about 10MHz by adding/moving EMI components in the circuit (like Y caps, etc.), but above there, it was just an absolute cacophony, noise visible at all locations, all angles, anywhere in the circuit, even some feet around the circuit! It was literally unworkable. The only solution I had was to re-lay the circuit, with ground planes this time. EMI dropped by over 20dB, and EMI components were effective up to, I forget what, 60, 90 MHz, something like that. Much more workable.
Tim
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