PCB Review - 24-bit ADC

[paeion]

Hi all,

Was hoping to get some general PCB feedback on the 24-bit ADC board I am working on. This is my first proper PCB design so I have slowly been learning from application notes, datasheets, similar projects and so worth...

Quick summary:
Trying to maximise the accuracy obtained from the TI ADS1256 24-bit ADC for measuring four load cells at around 1000Hz. Interfacing with an ESP32 MCU because of the in-built bluetooth to then communicate with the PC. The plan is to mount the ESP32 antenna on the exterior on the metal enclosure to act as shield. Also added a crowbar circuit for over-voltage protection on the input jack.

The board is four layers and split up as:
Layer 1: Signal – 5V/ 3.3V
Layer 2: Ground
Layer 3: 5V/ 3.3V
Layer 4: Signal – Ground

Main concerns:

• Decoupling/ bypassing on power and lCs (note ratiometric configuration)
• General layout recommendations to reduce digital noise coupling into the analog side, including my current crystal oscillator layout
• The shield routing for terminating the load cell shield cables via star-grounding to the metal enclosure
• Any major 'gotchas' in my design that will cause trouble

Attached are the schematic, pcb layers and 3d view of the board, any feedback would be extremely welcome!

[uer166]

General comment about GND planes: don't split the GND planes, have one, continuous ground plane for both digital and analog. The practice of doing what you did here in an attempt to get a star GND is not very helpful, and only improves the situation if the layout is already screwed up. It's out-dated, and while datasheets talk about doing that, it makes it worse in general. Instead, make sure all the digital traces (that run over the same GND plane as analog stuff), are physically separated laterally from analog path. Either directly terminate the shield at this one GND plane, or, if you are worried about circulating DC-current, AC-couple it to GND plane via a cap.

Do filter AVDD just like you did, since the AVDD rejection is less than DVDD rejection by a solid 30-40dB in this chip. Depending on the frequency content of the power rail you may want more, or less filtering. Layer 2 seems to be not GND also, make that GND and use L3 or bottom layers for the power planes, so you have a solid reference plane for everything. With that in mind you should get a good 16-18 bits ENOB given the signals use a reasonable dynamic range of ADC.

Edit: I mis-read your layer stackup and it seems that your ADC GND is same as digital, so all good there. You are missing AVDD filtering though, and only have it on the reference rail. I would reference the uh, VREFN rail to the one GND as well instead of putting it through the RC filter.

[paeion]

Thank you for the feedback, I will have a go with the shield termination you suggest and filtering on AVDD.

My layer description might have been confusing - the split planes on layers 1 and 3 are 5V (AVDD) and 3.3V (DVDD). Layers 3 and 4 are solid ground planes minus some short signals on the bottom.

Do you recommend switching the layer stack-up?

[moffy]

About, the I assume screw terminals? Screw_12 and Screw_34 how do the cables enter the terminals, from the top or the side?

[paeion]

Correct moffy they are screw terminals - was thinking on the side and I split up the load cell excitation/ signals to keep the analog input traces as short as possible.

I was confused about the RC filter on the VREFP and VREFN pins of the ADC (got it from the datasheet, pg. 28: https://www.ti.com/lit/ds/sbas288k/sbas288k.pdf?ts=1642081137965&ref_url=https%253A%252F%252Fwww.google.com%252F).

I have 10 and 0.1uF decoupling on the AVDD pin of the ADC as well as 22uF, 100nF and 10nF on the output of the 5V regulator (LP2985) but I'm not sure if the size of the tantalum cap (C9) is large enough - should I pick a larger package here?

[moffy]

You could make C9, 47uF or 100uF if you like, datasheet says that larger is better as long as it meets the minimum ESR requirements. My question about the screw terminals is how you are going to get the wires into the terminals? Wouldn't you be better rotating them 90 degrees, moving them to the edge, and ensuring the cables have a clear and easy path?

[David Hess]

The single point ground issue was more important in the past when the analog-to-digital converter likely had singled ended signal paths so more care was needed to minimize common mode noise.  A typical load cell sensitivity might be 2 millivolts per volt so with 10 volts of excitation, that yields 20 millivolts full scale, or 1 microvolt per count at 20,000 counts which places considerable demands on precision.

Common mode RF suppression with RC networks is often added to the excitation and signal connections to keep RF out.  (1) Parallel resistance for a common 350 ohm strain gauge bridge is a little higher than 175 ohms (2) so a series resistance up to that added to each signal has little effect on performance, or use RF suppression beads.

I would also add a bypassed resistance in series with each shield connection to limit fault current.

(1) TDMA cell phones were a real problem for a while.

(2) It will usually be higher because of a temperature dependent resistance in series with the excitation to adjusts the sensitivity of the bridge with temperature to compensate for the change in modulus of elasticity with temperature.  This also makes it easy to identify the excitation and signal connections with resistance measurements.

[paeion]

You're right moffy I think aligning the screw terminals at the edge of the board is the smarter way to go, I have no pcb size constraints so can simply stretch to accomodate.

Thanks David you are spot on, I am using 2mV/V cells with 350 Ohm resistance albeit 5V excitation. I will add ferrite beads ahead of the low filter on the analog input signals as recommended (likely do the same on the input power jack to reduce incoming noise on the supply).

I am curious about shortening the load cell wires - they have 3m of unshielded wiring which is inconvenient and would be acting as noise pick-up antennas. I know that changing the wire length affects the load cell sensitivity, but can't this just be adjusted with matched series resistance on the differential signal pairs?

Edit: Do you recommend a resistor size for the series bypassing on the shield connections?

[moffy]

The wire length from the load cells shouldn't effect the sensitivity, at such low frequencies, it isn't acting as a transmission line. Whatever length of leads you have make sure they are twisted as this will reduce pickup i.e it reduces the area between the wires and therefore their inductance as well as susceptibility to magnetic and electrostatic pickup.(turns them into more common mode than differential signal).

[mariush]

I would change the SCR to something surface mount, don't have a to220 floating in the air.  Plenty of options if you need such strong SCR, for example maybe https://www.digikey.com/en/products/detail/littelfuse-inc/SJ6020NRP/8629148

You could probably find something better than a 1117 regulator ... some require a capacitor on the output with ESR within some range (ex 0.1 .. 1 ohm esr), others are stable with with ceramic capacitors... but there's so many regulators out there stable with ceramic capacitors...

[paeion]

Perfect I will be looking forward to trimming those load cell wires! The signal pairs are twisted as I understand so apart from lack of shielding they should be ok.

In retrospect the TO220 SCR wasn't the wisest pick (grabbed the first jellybean part I found), will look for a slightly cheaper one than the SJ6020 in SMD format.

I had some potentially better 3.3V regulator options (such as RT9080-33G-J5, AP2112 or BL9110) but the max. input voltages are lower than my 7V input source. Ideally I would cascade the 5V regulator with the 3.3V one, but I couldn't find anything 'cheap' that would suffice the current draw needs of the ESP32 and had good low noise performance (i.e. the expensive LT3045 from Analog Devices).

Not sure if it worth the additional parts count of doing series regulators, or just obtaining a low ESR capacitor for the output of the 1117.

[David Hess]

Thanks David you are spot on, I am using 2mV/V cells with 350 Ohm resistance albeit 5V excitation. I will add ferrite beads ahead of the low filter on the analog input signals as recommended (likely do the same on the input power jack to reduce incoming noise on the supply).

RF pickup can be through the excitation wires also, although there a series resistance should not be used because it would lower the sensitivity.

I am curious about shortening the load cell wires - they have 3m of unshielded wiring which is inconvenient and would be acting as noise pick-up antennas. I know that changing the wire length affects the load cell sensitivity, but can't this just be adjusted with matched series resistance on the differential signal pairs?

There really is not much to match, but the length of the excitation wires does have an effect on calibration because of the thermal coefficient of resistance of the copper.  Some load cells use a 6-wire cable with force and sense for the excitation to avoid this, or use a current for excitation.  With only a 3 meter cable, I think you can ignore this and shorten the cable as much as you like.

Edit: Do you recommend a resistor size for the series bypassing on the shield connections?

I am not sure there is a bad choice.  The only need is to limit the current through the shield to prevent damage.  I have seen values from 10s of ohms to a megohm used.

[gamalot]

I don't know what kind of load cell you are using, but I know that common load cells are C6 or even C3 grade, usually when their excitation voltage and ADC reference voltage are the same source, and their input/output impedance is low, so they do not really require special care in ADC circuit design.

I've even used SMPS in a product to power the load cells, intermittently power the load cells and ADC to extend battery life, and they have always worked fine.

[paeion]

The load cells are C3 grade, but the challenge is that they are 500kg rated so trying to get +- 0.1kg resolution means I need a total system noise-free resolution of 2uV peak-to-peak from the ADC.

I have made some layout changes as recommended, with some things still missing including removing that RC filter on the ADC reference and RF suppression on the load cell excitation lines. Admittedly, there is a lot of wasted space on the PCB but I thought keeping the routing from the screw terminals to the analog inputs symmetrical was best (do correct me if I am wrong).

I am wondering now if I should be be doing via stitching between the power and ground planes... I will pull back the power layers on the edges to be inside the ground planes as well.

[David Hess]

I have made some layout changes as recommended, with some things still missing including removing that RC filter on the ADC reference and RF suppression on the load cell excitation lines.

Maybe I missed it but it looked like the ADC reference was the load cell excitation to make a ratiometric measurement.  If that is the case, then any filtering on the ADC reference should have the same time constant as filtering on the load cell signal.  Using the same time constant for both allows maximum cancellation of reference noise.

I don't know what kind of load cell you are using, but I know that common load cells are C6 or even C3 grade, usually when their excitation voltage and ADC reference voltage are the same source, and their input/output impedance is low, so they do not really require special care in ADC circuit design.

I just assumed accuracy to support 20,000 counts which is about the realistic maximum and what I would design for if I had no better target.  When I worked in the industry, I thought of different grades as 5,000, 10,000, and 20,000 counts.

[paeion]

Thats a very practical way to think about it, 5000 counts was what I calculated although closer to 10000 would be ideal to get a stable decimal point reading.

Equivalent filtering on the excitation and adc reference in a ratiometric configuration makes a lot of sense, thank you for the tip David!

[gamalot]

If response time is not a concern, a simple software sliding window filter will do the trick.