Where did 5 V logic level come from?

[Richard Crowley]

I was just reading about the history of the TTL logic family, but there was no mention of how they arrived at 5 V as the VCC power (and nominal signal levels)?
Anybody know what led them to what seems like a rather arbitrary voltage? 
6V would have seemed like a more logical choice, but likely most logic wasn't capable of battery operation back in the early days.
Even today we still keep 5V as a standard in many places (like USB power) even though (internal) logic levels have dropped to ~3V and lower.
Of course modern logic (likely mostly implemented as CMOS) can operate on a range of supply/logic voltage, higher and lower than 5V.

[Lightages]

Pick a voltage,any voltage! I assume it was arrived at what was a reliable switching voltage for the silicon processes at the time. It probably had enough noise margin and allowed proper regulation of most power sources. That would be my guess.

[void_error]

EEVblog -> Google -> EEVblog... slingshot effect?

[KM4FER]

Hmmm...  Take 5V, add Vce of a passthrough regulator and you still have a little headroom from a 6V supply.  There were a lot of 6V supplies around back then.  I wonder?

Of course there were a lot of 250-300V supplies around too but they couldn't source much current.

[T3sl4co1l]

It's curious, as one can make perfectly serviceable logic by connecting pull-ups to C-E's, and supplying B-E through a series resistor.  So the output swings 0 to 2*Vbe or so, and the B-E is turned on and off, actively and symmetrically, with quite reasonable current.  This can run down to 2V just fine, and using unbuffered outputs, supports wired-AND.  I think early RTL or DTL was formatted like this, but 5V was already a standard by then.

One consideration is noise immunity.  If you're wire-wrapping everything, you don't really want to have to deal with keeping ground bounce well under 1.2V.  TTL's threshold band is almost 2V, which really isn't that much better.

But I suppose one should keep in mind, something hardly has to be perfect for it to become a de facto standard.  Indeed, some truly awful things have become impenetrable walls of tradition.  Take C programming for instance.

Another difference is TTL's input stage, which pulls up weakly.  Not only does this interface with weak pull-ups and open collector signals, it's been a tradition that bus signals be idle-high, so even if left un-driven (which is normal, during arbitration on multi-master buses), signals do not accidentally become active.  I don't know if PCIe does this, but even the last 2.5V PCI (and probably AGP as well?) continued in the tradition.

I believe there was also "high threshold DTL" or something like that, which is basically the thing I described, but with a 5V zener dropping input to the base (plus a B-E pulldown), so the threshold is a lot more.  And the pull-ups are sized for 15V operation.

Tim

[retrolefty]

I recall working on system using RTL logic (yea, I'm old) and that the Vcc was around 3.6vdc.

[coolioh]

First system I worked on (transistors, no chips) was -12v, then CTL logic with +4.8v and -2v - times change.....

[Jay_Diddy_B]

Hi,
5V logic has its roots in TTL circuits. Here is a TTL 2 input NAND gate:




When the inputs are high (logic 1) the base-emitter junctions of the input transistors are reverse biased. A silicon transistor base-emitter junction will conduct in the reverse direction at around 6V. by using 5V the designers did not have to worry about reverse b-e breakdown.

Here are the waveforms:



 
Lower voltage came with CMOS. Power dissipation is proportional to 1/2 C * V * V * F

Power dissipation occurs when you charge and discharge the gate capacitance.

moving from 5V to 3.3V power dissipation drops to (3.3 x 3.3) / (5  x 5) = 10.9 /25 or 44% for the same clock speed.

Regards,

Jay_Diddy_B

[coppice]

I recall working on system using RTL logic (yea, I'm old) and that the Vcc was around 3.6vdc.

Yes, all the various RTL families I know of ran at 3.6V. When DTL appeared 3.6V was insufficient. The original discrete DTL used split supply rails, but they wanted a single rail for the integrated DTL gates. This required 2 more diode drops over the 3.6V of RTL, so they needed something around 5V and settled on exactly 5V. TTL followed the DTL supply voltage, as its needs were similar. They certainly didn't want to use 6V. It would have driven up dissipation for no benefit. ECL had different constraints, and most ECL used -5.2V for reasons I'm not too clear about. When the first MOS devices appeared TTL was so well established that being compatible was a big deal. Most early MOS ran from +12V, +5V and -5V rails, and faked a TTL interface.

5V I/O is a pain for fine geometry devices. Most MCUs still have 5V tolerant I/O pins, as a lot of people, especially in automotive and white goods, demand the noise margin a 5V swing offers them. However, the latest MCUs are starting to drop 5V I/O completely.