EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: hamdi.tn on December 24, 2015, 01:13:15 pm
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Hi, for a board passing from functional prototype to pre-production prototype, i been asked to add test points on the board. while i usually add test pad for debugging purpose , this will be the first time i have to add test point for production purpose ,and am completely noob about how exactly this is done, so am having a bit of problem on how to add those test pad on the PCB.
questions are
-Most guide about this, say that every node should be tested , this is insane for me. it will take more than 800 test point on my board, so i limit my choice to block functional testing strategy, is this OK.
-what can / can not be measured (are main AC voltage acceptable)
-If i choose to put my test points on bottom layer would the wave soldering ruin the contact surface for the test probes.
Any recommandation, tips , technical details are welcome :D
Thanks
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100% test coverage annoys me just because it wastes so much damn board area. ::)
The ideal is to be able to test each pin connection on the board, thus finding solder or component defects. Initial testing can be performed with a standard flying probe machine. Additionally, a production test jig can be assembled easily.
Basic testing is done by connecting a few suitable pins at a time, such as opposite ends of a given resistor, or the supply, ground and port pins of a logic chip, and asserting a voltage or current to prove that it is working (drawing a current through a resistor, exercising the VCC/GND diodes in a logic chip, etc.). (At least, that's what I assume they do. I'm not clear on the actual methods. I wouldn't think they can fully test everything, as it would be quite difficult to calibrate and measure a 5pF chip capacitor against the jig or probe capacitances.)
It's also compounded by another request: logic inputs and outputs should be separated by resistors, so they can be tested individually. Which basically multiplies your test points by N, for all applicable nets (e.g., SPI/I2C buses; lord help you if you have an old school parallel bus to test!).
The purpose of this testing is to provide early feedback for assembly and rework, and the beginnings of functional testing. I would suggest talking with the people responsible for the test; if it's reasonable to hit all these goals with a functional or operational test instead (e.g., if an attached LCD display starts up correctly and displays all colors with no error patterns, then its connector is proven good at a glance). A comprehensive test plan would have to analyze all nets; inevitably there will be some that are difficult or tedious to verify operationally, and would be better exercised with a test jig.
Tim
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In one sense, the time and effort (and board space) that goes into the test setup is balanced by the time and effort of rework. A complete node-by-node test takes a lot of work to design and implement, but makes rework pretty much a matter of doing what the test report tells you to. On the other hand, a simple functional test takes little effort to design and might give you a complete pass/fail at a glance, but means that rework requires extensive understanding of the circuitry in order to isolate failures (which means time) to their assembly-level causes. If you want to land somewhere in the middle, concentrate on the nodes that will help differentiate faults to isolate rework effort. Obviously that depends a lot on the complexity and architecture of the board. From this perspective, the effort that ought to go into the test setup is a function of production quantity because you're amortizing design engineer time that goes into the test design against the assembly tech time that goes into rework.
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100% test coverage annoys me just because it wastes so much damn board area. ::)
this what annoy me too.
In one sense, the time and effort (and board space) that goes into the test setup is balanced by the time and effort of rework. A complete node-by-node test takes a lot of work to design and implement, but makes rework pretty much a matter of doing what the test report tells you to. On the other hand, a simple functional test takes little effort to design and might give you a complete pass/fail at a glance, but means that rework requires extensive understanding of the circuitry in order to isolate failures (which means time) to their assembly-level causes. If you want to land somewhere in the middle, concentrate on the nodes that will help differentiate faults to isolate rework effort. Obviously that depends a lot on the complexity and architecture of the board. From this perspective, the effort that ought to go into the test setup is a function of production quantity because you're amortizing design engineer time that goes into the test design against the assembly tech time that goes into rework.
am planning on adding enough test points for each circuitry block of the board doing a particular task, that can't be detected by a final functional test (as T3sl4co1l said , an LCD will be sufficient to see if it work is enough proof that connection is good) or by self diagnostic once board is running. this reduce test pad from 800+ to 150-.
Thanks everyone :D
I would suggest talking with the people responsible for the test
am trying to find that guy here in the blog ::) am trying to get advice about what should be avoided and what are the limitation.
for now i added pads as explained in a 2.54mm grid 0.9mm diam pads. so this is a standard by all ppl that do tests. what am not sure about is the impact of wave soldering on those pad, does make them inusable for tests.
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You need to have some information first :
- bottom side on;y or top and bottom side ?
- pitch ?
- needle size ?
That will determine how close together you can space them and what the pad size needs to be.
Most pcb tools have automatic test point insertion.
It's not that difficult. If done properly it does not really consume a lot of spce either. Vias can be used as testpoints. Every board i do requires 100% coverage
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You need to have some information first :
- bottom side on;y or top and bottom side ?
- pitch ?
- needle size ?
already made my choice on that :
-bottom side ( my question is does wave soldering impact the quality of pad to needle contact in a way that make it impossible to test )
-2.54mm pitch
-0.9mm pad
Most pcb tools have automatic test point insertion.
you mean CADs ? cause am using altium and it does not have any automatic test point insertion
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If you use un-tented vias (with a solder mask opening) then you've basically got a makeshift test point on every net where there's an outside via.
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I would suggest talking with the people responsible for the test
am trying to find that guy here in the blog ::) am trying to get advice about what should be avoided and what are the limitation.
for now i added pads as explained in a 2.54mm grid 0.9mm diam pads. so this is a standard by all ppl that do tests. what am not sure about is the impact of wave soldering on those pad, does make them inusable for tests.
That will depend on the finish you get from the wave and the acceptable flatness for the test plane, these are questions for the people doing your testing as they are very specific and may change if any of the board/assembly/test house change. I've worked in companies that require 100% coverage of all nets before and after placement and companies with no electrical tests of the boards before functional test, practices can vary wildly in the real world.
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You can order a removable cover layer during wave soldering so your unsoldered exposed pad comes out clean for probing after the cover is peeled off. (My wife worked at a PCB firm at the CAD/CAM office, she knows about everything about PCBs except this, surprisingly!)
Besides vias, you can put probe-sized "holes" in the stop layer everywhere above your traces to allow probe access. You can consider 0 Ohm jumpers which allow for simplified short circuit hunting. If you intend to cut traces, reserve areas for the knife so it doesn't cut neighbouring traces. label important test points with cooper or silkscreen.
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You need to have some information first :
- bottom side on;y or top and bottom side ?
- pitch ?
- needle size ?
already made my choice on that :
-bottom side ( my question is does wave soldering impact the quality of pad to needle contact in a way that make it impossible to test )
-2.54mm pitch
-0.9mm pad
You dont get to make that choice. You need to talk to your assembly house or testing hOuse to see what their machines can do. And what the cost per needle is ( smaller pitch / finer needles cost more money ). These machines also have limitations in terms of needles per side , so you may have to use both sides.
Dont 'assume' !
Most pcb tools have automatic test point insertion.
you mean CADs ? cause am using altium and it does not have any automatic test point insertion
[/quote]
:palm: Yes it does. You need to set up the rules then launch the test point manager
http://youtu.be/oxfZhTHDCe4 (http://youtu.be/oxfZhTHDCe4)
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Old reference:
http://seventransistorlabs.com/Monitor/Images/PSU1.jpg (http://seventransistorlabs.com/Monitor/Images/PSU1.jpg)
Sony made SMPS, single sided phenolic PCB. Note that several large traces/pours have random pads on them, without through holes. These are in fact only soldermask openings. You can't see in the picture, but on closer inspection, there's even a recognizable pinprick in the middle of each one.
So, I'm quite certain they did a bed-of-nails production test on this thing, and that they used simple conical tip pins to do it. :)
If you have a reflow process, either leave the paste off, or try to make sure the flux is well cleaned away. I've seen crusty deposits (that didn't wash away on a normal pass) on DNP parts before, and the results would be similar for test points.
This shouldn't be a problem for wave.
Much more recent reference, HP/Compaq 8510W motherboard:
http://seventransistorlabs.com/Images/8510W_1.jpg (http://seventransistorlabs.com/Images/8510W_1.jpg)
http://seventransistorlabs.com/Images/8510W_2.jpg (http://seventransistorlabs.com/Images/8510W_2.jpg)
Notice almost all the vias are filled/capped, except for a few that are conspicuously soldered instead. I don't recall if a dimple is visible on them, but they are clearly intended for testing as well. Other trivia: PCB was made with OSP; solder is lead free (and spreads less, as is visible in other places); component glue used to mark assembly variant legend; etc.
As for Altium, check Tools / Testpoint Manager (towards the bottom). You can auto-assign fab and assy test points, but you need to define the rules for them first. If you shotgun them this way after placement, you'll probably end up with a lot of component pads or inappropriately sized/positioned vias chosen instead, so do be careful to sort them out first. (Using specifically sized vias/pads is a good idea, or using a dedicated single-pin component, which allows you to enforce test point coverage from the schematic level.)
The biggest downside to casual routing vias is, they're on the small side. It costs more to target smaller pads, and smaller pins have shorter lives.
I normally use 30 mil (minimum) pads, optional hole, 50 mil (minimum) spacing. 40 and 80 (respectively) happen more often (due to larger targets and grid spacing).
If you use SMT pad test components, you can add the "optional hole" by placing an appropriate size via in the middle. Remove paste from the pad, and it won't solder or fill.
I think holes are preferable for prototyping purposes, as you can get traditional 28AWG wirewrap wire inside a >= 12mil hole. (Even larger, and you can potentially fit an insulated wire through, for layer crossing patches, should the need arise!)
Tim
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Dont 'assume' !
got it :-+ will contact the concerned ppl
:palm: Yes it does. You need to set up the rules then launch the test point manager
i know about that tool. i think it's misleading to call it 'automatic' insertion tool.
it will choose via or pad or whatever you define on the rule. so if it can't find an appropriate via to use, the soft will not do any extra effort to insert via in a suitable position. the only thing that do is to check "test point " to manually added via or pad.
i expected more 'auto' in the automatic part of it :P
Old reference:
http://seventransistorlabs.com/Monitor/Images/PSU1.jpg (http://seventransistorlabs.com/Monitor/Images/PSU1.jpg)
Sony made SMPS, single sided phenolic PCB. Note that several large traces/pours have random pads on them, without through holes. These are in fact only soldermask openings. You can't see in the picture, but on closer inspection, there's even a recognizable pinprick in the middle of each one.
So, I'm quite certain they did a bed-of-nails production test on this thing, and that they used simple conical tip pins to do it. :)
If you have a reflow process, either leave the paste off, or try to make sure the flux is well cleaned away. I've seen crusty deposits (that didn't wash away on a normal pass) on DNP parts before, and the results would be similar for test points.
This shouldn't be a problem for wave.
Much more recent reference, HP/Compaq 8510W motherboard:
http://seventransistorlabs.com/Images/8510W_1.jpg (http://seventransistorlabs.com/Images/8510W_1.jpg)
http://seventransistorlabs.com/Images/8510W_2.jpg (http://seventransistorlabs.com/Images/8510W_2.jpg)
Notice almost all the vias are filled/capped, except for a few that are conspicuously soldered instead. I don't recall if a dimple is visible on them, but they are clearly intended for testing as well. Other trivia: PCB was made with OSP; solder is lead free (and spreads less, as is visible in other places); component glue used to mark assembly variant legend; etc.
As for Altium, check Tools / Testpoint Manager (towards the bottom). You can auto-assign fab and assy test points, but you need to define the rules for them first. If you shotgun them this way after placement, you'll probably end up with a lot of component pads or inappropriately sized/positioned vias chosen instead, so do be careful to sort them out first. (Using specifically sized vias/pads is a good idea, or using a dedicated single-pin component, which allows you to enforce test point coverage from the schematic level.)
The biggest downside to casual routing vias is, they're on the small side. It costs more to target smaller pads, and smaller pins have shorter lives.
I normally use 30 mil (minimum) pads, optional hole, 50 mil (minimum) spacing. 40 and 80 (respectively) happen more often (due to larger targets and grid spacing).
If you use SMT pad test components, you can add the "optional hole" by placing an appropriate size via in the middle. Remove paste from the pad, and it won't solder or fill.
I think holes are preferable for prototyping purposes, as you can get traditional 28AWG wirewrap wire inside a >= 12mil hole. (Even larger, and you can potentially fit an insulated wire through, for layer crossing patches, should the need arise!)
Tim
thanks tim really helpful :D