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Electronics => Projects, Designs, and Technical Stuff => Topic started by: promach on June 10, 2020, 12:01:08 pm

Title: Phase margin plot of LDO
Post by: promach on June 10, 2020, 12:01:08 pm

For this LDO circuit design at https://github.com/promach/LDO/tree/development ,

1) which exact circuit node(s) contributes to the zeroes near 1MHz after removing CL ?

2) If I remove "AC 1" from Vref, why the whole bode plot becomes erratic ?

(https://i.imgur.com/H12f2w1.png)

(https://i.imgur.com/ZLlzQgC.png)