Author Topic: Phase margin plot of LDO  (Read 457 times)

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Offline promachTopic starter

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Phase margin plot of LDO
« on: June 10, 2020, 12:01:08 pm »
For this LDO circuit design at https://github.com/promach/LDO/tree/development ,

1) which exact circuit node(s) contributes to the zeroes near 1MHz after removing CL ?

2) If I remove "AC 1" from Vref, why the whole bode plot becomes erratic ?



 


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