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PIC silicon bugs - ADC offset


I was looking for a high pin-count PIC and one good looking option was the PIC18F66K22. It's a very capable device, yet costs only £2.99 in single quantities. I thought I was lucky, until I checked the Silicon Errata and found this:

--- Quote ---1. Module: Analog-to-Digital Converter (A/D)
The ADC will not meet the Microchip standard ADC specification. ADC may be usable if tested at the user end. The possible issues are high off-set error, high DNL error and multiple missing codes. The ADC can be tested and used for relative measurements.

The ADC issues will be fixed in a future revision of this part.

ADC Offset
The ADC may have high offset error up to a maximum of 50 LSB; it can be used if the ADC is calibrated for the offset.

Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect ADC +ve input to ground and take the ADC reading. This will be the offset of the device and can be used to compensate for the subsequent ADC readings on the actual inputs.

--- End quote ---

ADC is vital for my project and now I'm puzzled. Has anyone dealt with ADC offsets? I could use the suggested workaround if the same offset applies to all the channels (dedicating one channel for automatic calibration). The other option would be to buy a separate SPI ADC, but that results in extra costs.

Also, what does 50 LSB mean if the ADC resolution is 12 bits?

P.S. Selecting different device doesn't seem to be an option. All reasonably-priced chips belong to the same family and non-K equivalents are about twice as expensive (plus got other silicon bugs).

I think they are trying to say that the error may be of 50 (maximum reading is 4096), so a converted number could be offset by 50. the channels usually use the same ADC that is switched from channel to channel

1 LSB = 2^(-12) * Vref

Thanks for the replies, it makes sense now.


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