Author Topic: DDS Function Gen Layout Review  (Read 15826 times)

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Offline PCB.Wiz

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Re: DDS Function Gen Layout Review
« Reply #100 on: November 07, 2023, 10:15:39 pm »
Revisiting using a heatsink on the LM7171... as you noted I may also be better off with the DIP package to better be able to transfer heat into the board. Big reason I'm making this breakout board is to be able to see what is required thermally for LM7171, as I'd really like to get 5Vp-p unless it becomes apparent that would require an excessive amount of effort.

Are all opamps this way? What intrinsic parameters of the opamp typically contribute to higher heat (GBW, etc)? Is the signal of the op-amp relevant to the energy consumption, or just the gain, or both?

The power loss depends on supply voltage, load swing, and load resistance. It's a classic class-B power vs signal level.

This is worst case - appx 64% full swing, where I and V intersect at 50%


Note here they show power per transistor, your Opamp has two transistors, so the green line doubles to average 0.4, or 80% of the peak.
A rough calc indicates about 450mW which is a lot for a SO-8 and will need agressive maximum copper
 
« Last Edit: November 07, 2023, 10:31:31 pm by PCB.Wiz »
 

Offline PCB.Wiz

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Re: DDS Function Gen Layout Review
« Reply #101 on: November 07, 2023, 10:30:29 pm »
Where in the goldilocks scale is this? Still too little, too much, or somewhere in between? Vcc/Vee highlighted in red, and all GND and NC are connected to the ground pour without thermal reliefs where feasiblee
You can never have too much  8)

Not bad, but I'd certainly move the output resistor R7 and greatly increase its size.
It also generates significant heat, keep it well away from the opamp !

Double sided copper can help too, with liberal thermal vias to get heat into the other side.
You can also increase the copper flow from VCC


Here is SO-8 2oz copper area vs thermal max indications, more copper is better



« Last Edit: November 07, 2023, 10:42:27 pm by PCB.Wiz »
 

Offline jgrossmanTopic starter

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Re: DDS Function Gen Layout Review
« Reply #102 on: November 10, 2023, 04:00:46 am »
Any other suggestions before I get this BOB manufactured? I've attached a PDF of the schematic again for reference, but it's 99% identical as before, just made it so there is a single jumper for the boost+inverter selection

1923807-0
 

Offline jgrossmanTopic starter

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Re: DDS Function Gen Layout Review
« Reply #103 on: November 10, 2023, 04:43:48 am »
Where in the goldilocks scale is this? Still too little, too much, or somewhere in between? Vcc/Vee highlighted in red, and all GND and NC are connected to the ground pour without thermal reliefs where feasiblee
You can never have too much  8)

Not bad, but I'd certainly move the output resistor R7 and greatly increase its size.
It also generates significant heat, keep it well away from the opamp !

Double sided copper can help too, with liberal thermal vias to get heat into the other side.
You can also increase the copper flow from VCC


Here is SO-8 2oz copper area vs thermal max indications, more copper is better


Is the same volume of 1oz copper over 2x the area approx. equivalent?
 

Offline PCB.Wiz

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Re: DDS Function Gen Layout Review
« Reply #104 on: November 10, 2023, 05:56:33 am »
Is the same volume of 1oz copper over 2x the area approx. equivalent?
It will not quite be as good, as the heat needs to travel sideways, but a larger board will radiate more heat into the air than a smaller board.
PCB houses tend to charge an adder for 2oz, so most prototypes use 1oz copper.
This design is not many-watts so you should  be ok.

In your design I might duplicate the power copper areas on the reverse side, at least for 20~40mm, and add thermal vias to those areas.
The heat then transfers across a larger area to the larger GND planes.
Also, place the thermal vias closer to the SO-8 package. You want both side to be working for you.
 

Offline jgrossmanTopic starter

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Re: DDS Function Gen Layout Review
« Reply #105 on: November 10, 2023, 08:23:03 am »
Decided to just respin this BOB layout, it was easier to incorporate the feedback with it in mind from the start:

1923903-0
« Last Edit: November 10, 2023, 08:32:27 am by jgrossman »
 

Offline jgrossmanTopic starter

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Re: DDS Function Gen Layout Review
« Reply #106 on: November 13, 2023, 02:17:58 am »
I think I'm closing in on what I'm going to get manufactured.

Here is updated schematic + layout:

1926762-0
« Last Edit: November 13, 2023, 03:21:30 am by jgrossman »
 

Offline jgrossmanTopic starter

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Re: DDS Function Gen Layout Review
« Reply #107 on: November 13, 2023, 04:29:50 am »
As it is laid out right now, it still passes ERC without the inner ground layers. I'm thinking about dropping them for cost (I must have done something wrong when looking before, or my board sized changed enough, but JLCPCB is more expensive by 4x for 4 layers), but am worried about some stuff:

  • The inner layers may provide a non-negligible amount of thermal mass around the LM7171, even with only inner 0.5Oz Cu. I'm not sure how much, if it all, this will matter.
  • I'm worried my bottom ground has been chopped up too much. I tried to keep the length of my bottom traces as short as I could anticipating the possible removal of the inner layers, but especially the 3.3V for the DDS is kindof way out by itself and I struggled to find another way that didn't meander around the whole board:

    1926852-0

    1926825-1

  • I know this isn't a high speed board by most definitions, but worried about signal integrity without the support of the inner layers. I'm sure a more experienced engineer could do just fine with 2 layers, but that's not me  :-X
« Last Edit: November 13, 2023, 05:26:29 am by jgrossman »
 

Offline PCB.Wiz

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Re: DDS Function Gen Layout Review
« Reply #108 on: November 13, 2023, 07:22:18 am »
As it is laid out right now, it still passes ERC without the inner ground layers. I'm thinking about dropping them for cost (I must have done something wrong when looking before, or my board sized changed enough, but JLCPCB is more expensive by 4x for 4 layers), but am worried about some stuff:

If you can fit on 2 layers, you can keep the 4 layer design for the final pass, as this is a prototype, and likely to change.

Thermally, it is looking quite good, you could maybe get some thermal vias under the SO-8 packages.
You are not trying to cool many-watts here.
 


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