The reason only inverting configurations are shown is revealed in the specifications if you know where to look. The common mode rejection is a horrible 45dB *typical* or 1:178 so for every volt of change in the non-inverting input, the input offset voltage changes by 5.6 millivolts, and it could be *worse* than that. (1) The poor common mode rejection comes from having a rail-to-rail input and being produced on a digital CMOS process. The other DC specifications are equally poor as expected.
(1) This cannot be treated as a gain error because it is non-linear.