I have an application where I want to clean up the noise from a switching converter and putting large amount of capacitors on board isn't really a viable option size and power dissipation limited
. A capacitance multiplier seem like a good space and cost effective way to do this. However the current draw has the potential to swing over a wide range. To throw some real number this say 10ma to 1000ma @~24V. Now in the situation where I'm drawing less than ~50mA I want really good noise rejection but as the current increases I care less about the noise rejection and become more concerned with the heat build up in the transistor. So I would like to reduce the effective R value in the multiplier raising the bias current as output current increases. However the only ways I can currently think to do this is with a rather convoluted series of opamps and I would think there is a more elegant way to do this. Anyone know of a topology that would allow a function like this?