Author Topic: how to build a capacitance multiplier with variable bias current  (Read 517 times)

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Offline qwaarjetTopic starter

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how to build a capacitance multiplier with variable bias current
« on: September 12, 2019, 04:55:31 am »
I have an application where I want to clean up the noise from a switching converter and putting large amount of capacitors on board isn't really a viable option size and power dissipation limited :'(. A capacitance multiplier seem like a good space and cost effective way to do this. However the current draw has the potential to swing over a wide range.  To throw some real number this say 10ma to 1000ma @~24V. Now in the situation where I'm drawing less than ~50mA I want really good noise rejection but as the current increases I care less about the noise rejection and become more concerned with the heat  build up in the transistor. So I would like to reduce the effective R value in the multiplier raising the bias current as output current increases. However the only ways I can currently think to do this is with a rather convoluted series of opamps and I would think there is a more elegant way to do this. Anyone know of a topology that would allow a function like this?
 

Offline Whales

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Re: how to build a capacitance multiplier with variable bias current
« Reply #1 on: September 12, 2019, 06:01:10 am »
Shunt resistor to measure current draw -> optocoupler -> bias ?

You may want to pre-bias  the optocoupler somehow so you don't need as much Vdrop across the Isense resistor.


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