| Electronics > Projects, Designs, and Technical Stuff |
| Please help design discrete JFET preamplifier |
| << < (4/5) > >> |
| Zero999:
You have conflicting requirements. J-FET noise and capacitance are related. To get lower noise, the gate junction ares needs to be increased, but that also increases the capacitance. |
| T3sl4co1l:
What is the source? 20mV isn't a very small signal. What dynamic range are you after? Tim |
| Kleinstein:
A 1 Mohms divider also has some noise on it's own. So if possible I would avoid dividing the signal all the way down to 20 mV. For a low noise and low input impedance amplifier there are a few articles from NIST/NBS about a rather similar amplifier. To reduce the input capacitance they use bootstrapping the FET. |
| iMo:
Here a few simulations. Not sure about the noise simulation, however. |
| magic:
In my experience LTspice reports voltage noise contribution of transistor input stages as the theoretical minimum: shot noise of collector current divided by transconductance. AFAIK it's mostly correct at high frequencies unaffected by 1/f noise. edit Until you run into Johnson noise of the base/gate parasitic resistance. Dunno if LTspice has models of that. |
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