They show what the address pins map to, but without a spec on propagation delay (if it's different at all, for changes in different address pins), it's only trivia. Treat all the address lines as equivalent and interchangeable (which is actually true: you don't need to know what the address is inside the chip, as long as you use the same pins for programming and reading).
For a Z80, hook up the data and address pins, and use the upper address pins from the CPU to operate an address decoder (usually a 74LS138, 154 or something like that) which drives the \CS pin. You also want to take IORQ/MEMRQ and RD/WR through the appropriate logic (using the decoder's inputs, or more gates, however it works out).
You can compare the timing diagrams; you should find they are quite compatible, and the timings work out nicely without wait states. If you have period DRAM, you will need more decoding logic (RAS/CAS strobes) and a few wait states to insert for strobe/access delays. A DRAM controller might provide these for you (as well as refresh, DMA or other possible features).
Tim