suggest me how to block ESD injected on the power line

[mcinque]

Hello all,

my circuit has 2 entry points for esd.

I've filtered properly (at least, I guess since it's working) with a TVS the entry point #1  - a push button - but I can't find a solution for the entry point #2, that is an on/off key switch that drives the positive rail.

Without a proper clamping on the entry point #2 all the other protections are useless since the pulse goes thru all the positive rail.

Of course here I can't use the TVS+RESISTANCE+CAPACITOR, because with the series resistance I have a lot of voltage drop and current limiting.

Can you suggest me a possible solution?

A low pass filter could be enough? I think I need to clamp most of the energy to ground and to use the filter only for the remaining pulse.

Any thought is appreciated!

[SeanB]

LC filter before the TVS diode. and place a damping resistor across the inductor, or use a very lossy ferrite material.  You can add extra LC sections to each switcher input as well. Use inductors with low DC resistance, and inductance of between 100- 470uH capable of passing the required current. Likely not toroids but only use open coils. Capacitors will be rated to handle output current of the switchers, as that is what they will be supplying.

[Precipice]

Does your 14.8V battery imply an automotive application? If so, you'll have a lot more than ESD to worry about.

However - power lines are normally very easy to protect from ESD. A few fast capacitors to ground, and a bit of inductance, and you'll be fine.
Remember that the ESD source is a tiny capacitor - a bigger capacitor for it to empty its charge into will divide that potential right down.

Your drawing shows ESD paths _through_ your regulators. That can't possibly be a good thing.

[mcinque]

Thank you for your replies

I've redrawn the schematic, using only one LC and no extra ones at every regulator input (at the moment).

EDIT: it works fine.

Does your 14.8V battery imply an automotive application? If so, you'll have a lot more than ESD to worry about.

Luckily, this is not an automotive device.

Remember that the ESD source is a tiny capacitor - a bigger capacitor for it to empty its charge into will divide that potential right down.

You're damn right.

Your drawing shows ESD paths _through_ your regulators. That can't possibly be a good thing.

Those was unwanted discharge paths due to lack of protection 

[SeanB]

I would suggest adding a second inductor to the circuit to only feed the load side, along with the TVS and capacitors, so as to reduce noise from switching getting into the supply rails. What value capacitors are you using, I am guessing with the 14V4 you are using 4 series 18650 cells.

[mcinque]

Thank you for the advice, I will surely add it, good thought!

At the moment I'm using 4 x 3.7 LiPo cells, but the also 18650 would work fine.

For the filtering capacitors behind the TVS I'm using ceramic .1uF for the ESD entry 2, and I guess that I could use the same value for the 1st entry but honestly I don't know exactly wich value to use for the LC filter. For wich frequency cut should I calculate the capacitor?

[DanielS]

For ESD coming from power sources, you can simply put a moderate-size cap from ground to V_In - you need that bulk decoupling cap to filter the power source and cable inductance anyway if you do not want inductive kick from the source to kill your components when something goes wrong (momentary short) between your source and your board or your board draws a significant momentary peak for some reason. The linear regulator requires a 10-100µF cap on the input anyway.

You should not need to worry (much) about ESD on power inputs since the capacitive voltage divider between the ESD source' 1-2nF and the board-level decoupling's 10+µF will drop ESD voltage on the power rail to less than 1V as long as the ESR+ESL is low enough. If you are really that worried about ESD on the power input then you can use a TVS + inductor before the bulk cap.

As far as the filter inductor is concerned, the inductor only needs to be large enough to take the edge off the ESD to give the TVS more time to clamp it and reduce the voltage rise across the capacitor's ESR+ESL so you only need something like 10µH. For the capacitor, your existing board-level power input decoupling (likely well over 10µF) should be enough if you used a few MLCC caps.

[mcinque]

Thank you DanielS, very clear and instructive