Please recommend a VGA to parallel LCD board or IC

[avst]

It is clear that I need to put much more effort and focus to learn porch, APLL and DPPL modification programming

The steps these firmwares take are more or less:

• Detect the signal (activity on sync signals)
• Measure availabe data: Vtotal, Hor. frequency, Ver. frequency, sync polarity and sync width
• Lookup or calculate missing values, Htotal, Hstart and Vstart. Mostly done with a large lookup table. If there is not perfect match, take something similar
• With the Htotal value, the sampling clock can be determined to setup the source pll.
• From the values obtained, the input capture area (position and size) can be setup
• With the horizontal and vertical active, the scaling can be calculated
• From the scaling the pixel clock for the output can be calculated to setup the output pll
• Now the output interface can be setup and the LCD enabled. Note that the output timing varies depending on the input timing, and there are cases, where the output timing would be outside the LCD specs.
• Most often, the table or calculated values will not be perfect, so some fine tuning has to be done (HTotal, sampling phase and position).This is the auto adjust most firmwares offer. These differ from chip to chip, but all are image dependent, which is not 100% bulletproof. E.g. horizontal/vertical position may be deduced from the first non black pixel.
• Sometimes the ADC range can be auto adjusted, provided a suitable image is displayed.
• After everything is finished, the firmware monitors the input timing, to start the whole cycle again, if a significant change occurs

[Tantratron]

Regarding 15kHz operation, the chip is definitely capable of decoding video in that form, but no available firmware does it, as far as I know. The only example I know of is a 5 inch screen labeled Eyoyo, which at least supports 480i operation.

Hello @ahrlad, I've found this first thread discussing Eyoyo with interesting pictures and comments. But are you really sure this RTD2660H firmware does 480i or have you tried yourself ?
No where in the thread I clearly see this product to eat as an input an interlaced 15 KHz RGBS. It does mention YPbPr which is of your interest but that is only three signal input where the synchronization is embedded inside Y signal.
I've found recent details from Eyoyo in this page but I do not see clearly its capacity to deal with 480i or something close from my RGBs interlaced.

[Tantratron]

Here is an update regarding the same vendor from which I've ordered two PCB800099-V9 boards (one 5 december then another 20 december). I note one board has the RTD2660H chip sanded or hidden whereas the other is clearly marked. As a reminder from an old post and discussion, I put in the attached picture the 3 board which I had over-heating problems and no stable firmware execution. I'll see one of these days if that board can be fixed, I start to think the problem is one of its local power supply unless one PCB traces is at fault but comparing side by side some volatge shows a clear difference. One issue is the LDO in charge to generate the 1.8 V from the 3.3 V where if no power, my DMM will read very low value to GND on its 2 output pins. However when power on, it will make separate 1.8 V and 3.3 V on both output pins so this is really wierd. I suspect the switch buttons could be affected by this problem because their voltage result does control what the RTD2660 will do. I'll make later a specific thread to see if my 3rd board can be fixed but I'm attaching local view of this LDO.

Anyway i'm very happy with this model purchased here on AliExpress where the connectors are stronger, firmware stable, PCB neat soldering and price low. It is still not clear all the different jumpers possibilities versus which LCD display (attached two datasheet) but I have enough choice to inspect registers/scalers via my arduino sketch to consolidate my understanding on how to program the RTD2260H.

[ahrlad]

Regarding 15kHz operation, the chip is definitely capable of decoding video in that form, but no available firmware does it, as far as I know. The only example I know of is a 5 inch screen labeled Eyoyo, which at least supports 480i operation.

Hello @ahrlad, I've found this first thread discussing Eyoyo with interesting pictures and comments. But are you really sure this RTD2660H firmware does 480i or have you tried yourself ?
No where in the thread I clearly see this product to eat as an input an interlaced 15 KHz RGBS. It does mention YPbPr which is of your interest but that is only three signal input where the synchronization is embedded inside Y signal.
I've found recent details from Eyoyo in this page but I do not see clearly its capacity to deal with 480i or something close from my RGBs interlaced.

Hello!

No, I haven't used the screen myself and I couldn't say confidently that it'd support your signal. With both VGA and YpBpR the different firmwares compare the input to a list of known video formats, and yours probably wouldn't find a match.

[timeandfrequency]

Regarding my specific test to learn how to program different registers/scalers, as mentioned I've used now the VGA output signal from one of my TDS500/700 oscilloscopes. These were designed by tektronix in the early or mid 90's. When reading their theory of operation service manual, it is not clear where does the 800x480 resolution comes but it is a variant situation as with the Advantest SA of end of 80's, namely inside their video is digital generated then they down-size or degrade through digital to analog so drive either color or mono-CRT.
[...]
I'm attaching an extract from tektronix TDS500/700 regarding video part

The tektronix TDS500/70 SM excerpt provides some faint clues why the 800 x 480 resolution was chosen.
At least for the Ypixel value : the reason is probably to limit the amount of the expensive (usually dual port) VRAM.

page 1-24 : The waveform planes are 512 by 512 bit maps. Only the upper 480 lines are
displayed

480 Ypixels fit inside a 512 bit plane, so 640 x 480 (standard VGA) was probably the first goal, as stated by the second sentence below (about the text plane).

page 1-25 : Each text plane is a 1024 x 512 bit map with one bit per pixel. The upper
left-hand corner of the bit map, a 640 x 480 section, is sent to the RAMDAC.

I would say that after that first attempt, the Tek guys noticed that the text wasn't that readable, and to improve the situation, as no RT video processor was available inside the scope to do some digital sharpening, the only options left were using bigger fonts (meaning less contents displayed) or improve resolution.
With a 1024 x 512 bit map for the text plane they could push the Xpixel value to 800, but were stuck to 480 Ypixels.
A standard SVGA format of 800 x 600 required a 1024 x 1024 bit map, hence doubling the amount of VRAM to be put on the motherboard.
And perhaps, one boss said No.

With a 1024 x 1024 bit map, even XGA (1024 x 768i) and XGA-2 (1024 x 768p) that showed up in 1990 would have been possible.

The same Wiki page tells us that the 800 x 480 resolution has actually it's own acronym : it is WVGA (or WGA) and a dedicated name : 'Wide VGA' and that is was used for LCD projectors and later portable and hand-held internet-enabled devices.

[Tantratron]

It is clear that I need to put much more effort and focus to learn porch, APLL and DPPL modification programming

The steps these firmwares take are more or less:

• Detect the signal (activity on sync signals)
• Measure availabe data: Vtotal, Hor. frequency, Ver. frequency, sync polarity and sync width
• Lookup or calculate missing values, Htotal, Hstart and Vstart. Mostly done with a large lookup table. If there is not perfect match, take something similar
• With the Htotal value, the sampling clock can be determined to setup the source pll.
• From the values obtained, the input capture area (position and size) can be setup
• With the horizontal and vertical active, the scaling can be calculated
• From the scaling the pixel clock for the output can be calculated to setup the output pll
• Now the output interface can be setup and the LCD enabled. Note that the output timing varies depending on the input timing, and there are cases, where the output timing would be outside the LCD specs.
• Most often, the table or calculated values will not be perfect, so some fine tuning has to be done (HTotal, sampling phase and position).This is the auto adjust most firmwares offer. These differ from chip to chip, but all are image dependent, which is not 100% bulletproof. E.g. horizontal/vertical position may be deduced from the first non black pixel.
• Sometimes the ADC range can be auto adjusted, provided a suitable image is displayed.
• After everything is finished, the firmware monitors the input timing, to start the whole cycle again, if a significant change occurs

I've been following these different steps but for a few days, i'm stuck near going nuts regarding the first step detect the signal. As i've posted back, I thought to have easily found the instruction to identify if there is signal, what type of signal by reading the specific register/scaler 0x4C (see page 46 of the RTD2660) datasheet.

When the RTD board boots, no problem it will either work with RGBS 1264x525 15 KHz or VGA 1024x768 48 KHz or VGA 800x480 31 KHz so I enter into ISP mode via arduino I2C command, still no problem where I can read register 0x4C to extract the 3 bits (6:4) after checking bit 7 states Type Detection auto Run ready. The problem which i'm bumping my head, if I do stay in ISP mode (8051 is halted) then if I do change live the signal input type (i.e. VGA becomes RGBS or vice-versa) or no signal then the register 0x4C is never updated. It will keep the last former values found when 8051 did boot prior being halted by ISP mode.

I initially thought that register 0x4C is kind of always detecting HSYNC input type (co-processor or scaler slave) but unless I miss some additional programming, I was wrong. Before asking help here, maybe @KerJoe knows the answer, I've read different github repo (KerJoe     danyaPostfactum  and  specadmin). It seems more complex than what I thought, do you know a simple sequence of commands to update and detect type of input signal, what is necessary to do prior accessing valid detection from register 0x4C. Something similar to RestoreVGA() subroutine provided by KerJoe a while ago except here is to say restart steps described by avst.

The positive side of things, my reading many source files from these 3 repo kind of help me now clearly understand some concept, the key steps like once you capture some input frame info then you look for a database table to match close the values then find typical missing value. Of course my problem wether with the Advantest or the tektronix, bad luck where the resolution is not so standard but that is OK.

[avst]

The positive side of things, my reading many source files from these 3 repo kind of help me now clearly understand some concept, the key steps like once you capture some input frame info then you look for a database table to match close the values then find typical missing value. Of course my problem wether with the Advantest or the tektronix, bad luck where the resolution is not so standard but that is OK.

Maybe you could patch the mode into the modetable (modetable.h) in flash, the mode is prersent in YPbPr.h, but probably that is not enabled in your firmware. The values in that table are not used, if YPbPr is not enabled.

In YPbBr.h:

Code: [Select]

    {   // Mode 1 : 720 x 480i x 60 Hz
        0 | _SYNC_HN_VN | _SYNC_HP_VN | _SYNC_HN_VP | _SYNC_HP_VP,          // Polarity Flags,
        704-20, 224+8,                                                      // InputWidth, InputHeight,
        157, 600,                                                           // HFreq in kHz, VFreq in Hz,
        _HFREQ_TOLERANCE, _VFREQ_TOLERANCE,                                 // HFreqTolerance in kHz, VFreqTolerance in Hz,
        858, 262,                                                           // HTotal, VTotal,
        129+20, 22,//27,                                                    // HStartPos, VStartPos,
    },

Locating the table in the binary and patching the values shouldn't be to difficult. But you should not used the first few modes, because these get a special treatment in the firmware, as there are multiple valid resolutions for the same measurements (old legacy stuff). Maybe use the _MODE_640x480_66HZ entry, as this is another not very common resolution.

Code: [Select]

enum PresetModeDef
{
    _MODE_640x350_70HZ = 0,          // Mode 00: 640x350_70Hz, 720x350_70Hz
    _MODE_640x400_56HZ, // Mode 01: 640x400_56Hz
    _MODE_640x400_70HZ, // Mode 02: 640x400_70Hz, 720x400_70Hz
    _MODE_720x400_70HZ,              // Mode 03: 640x400_70Hz, 720x400_70Hz
    _MODE_640x400_701HZ,          // Mode 04: 640x400_70.1Hz
    _MODE_640x480_60HZ,              // Mode 05:
    _MODE_640x480_66HZ,              // Mode 06:
    ....


[avst]

I initially thought that register 0x4C is kind of always detecting HSYNC input type (co-processor or scaler slave) but unless I miss some additional programming, I was wrong. Before asking help here, maybe @KerJoe knows the answer, I've read different github repo (KerJoe     danyaPostfactum  and  specadmin). It seems more complex than what I thought, do you know a simple sequence of commands to update and detect type of input signal, what is necessary to do prior accessing valid detection from register 0x4C. Something similar to RestoreVGA() subroutine provided by KerJoe a while ago except here is to say restart steps described by avst.

The firmware seems to do following steps (sync.c):

• Start a stable measurement by setting bit 0 of reg 0x4F and wait 5ms
• Check if hsync is present by looking at hsync counter overflow, reg 0x4E, bit 7
• if no overflow, wait another 60ms, then check if signals are stable in reg 0x4F, bit 7
• if stable, reads the hsync counter, and programs it into reg 0x4C and 0x4D (some special cases are used here)
• Stops a stable measurement by resetting bit 0 of reg 0x4F
• Starts the auto measurement by resetting, and then setting bit 6 of reg 0x47

[Tantratron]

First of all, I wish everybody a Happy New year 2025.

Hello @avst thanks for your last 2 posts, in particular the 2nd one which helps me to clarify and understand the sequence of calling, polling to say self-detect signal presence then detects what type of VGA signal. I'll try later to code your findings and suggestions in my arduino sketch then will share the outcome.

One serious difficulty is how to absorb, understand the different source files. Some are the Realtek leaked files which seems very heavy, lot of cases, lot of lines and not so much comments inline. Then some person mainly from Russia on GitHub have tried to reverse engineer or understand or simplify the leaked source file to go after some autonomous source file. However many times, they offer even less comments or will cover only special case of signal (i.e. HDMI).

I believe you have mainly read the alien files section of KerJoe which seems close from Realtek leaked files.

As for mapping or patching some modes into my OpenRTD2662 running firmware, maybe it could solve the other issue of the RGBs deinterlacing firmware to hopefully solve the image cropping and less clear the more we go to the right of the LCD (i.e. vertical grid lines ddisappearing progressively). If only more projects were known to address specifically the 15 KHz deinterlacing or YPbPr modes versus more project doing VGA input or HDMI input.

Albert

[Tantratron]

I initially thought that register 0x4C is kind of always detecting HSYNC input type (co-processor or scaler slave) but unless I miss some additional programming, I was wrong. Before asking help here, maybe @KerJoe knows the answer, I've read different github repo (KerJoe     danyaPostfactum  and  specadmin). It seems more complex than what I thought, do you know a simple sequence of commands to update and detect type of input signal, what is necessary to do prior accessing valid detection from register 0x4C. Something similar to RestoreVGA() subroutine provided by KerJoe a while ago except here is to say restart steps described by avst.

The firmware seems to do following steps (sync.c):

• Start a stable measurement by setting bit 0 of reg 0x4F and wait 5ms
• Check if hsync is present by looking at hsync counter overflow, reg 0x4E, bit 7
• if no overflow, wait another 60ms, then check if signals are stable in reg 0x4F, bit 7
• if stable, reads the hsync counter, and programs it into reg 0x4C and 0x4D (some special cases are used here)
• Stops a stable measurement by resetting bit 0 of reg 0x4F
• Starts the auto measurement by resetting, and then setting bit 6 of reg 0x47

Ok it works now, many thanks again, see my source code extract (needs to be written more clearly and pro...) but works

Code: [Select]

int8_t AutoDetectInput(void)
{
uint8_t timeout_i, timeout=90;

// Reset auto sync detection
  ScalerWriteBit(0x4F, 0, 0b0);
  ScalerWriteBit(0x4F, 0, 0b1);
  delay(5); // wait 5 ms

//check if Hsync is present looking at hsync counter overflow
  if(ScalerReadBit(0x4E,7))
  {
    Serial.println("No Input");
    return(-1);
  }
  else
  {
    delay(60); // wait another 60 ms
    if(ScalerReadBit(0x4F,7)==0)
    {
      Serial.println("No stable measurement");
      return(-2);
    }
    Serial.println("Signal present");
    ScalerWriteBit(0x4F, 1, 0b1); // pop up stable value
  }
  Serial.print("Stable Hysnc period       => ");Serial.println(((ScalerReadByte(0x50) & 0x7) << 8) + ScalerReadByte(0x51),DEC);
  ScalerWriteByte(0x4C, (ScalerReadByte(0x4C) & 0xF8) | (ScalerReadByte(0x50) & 0x07));
  ScalerWriteByte(0x4D,ScalerReadByte(0x51));
  ScalerWriteBit(0x4F, 0, 0b0);  // stop stable measure
  ScalerWriteBit(0x47, 6, 0b0);
  ScalerWriteBit(0x47, 6, 0b1);  // enable hysnc type detection auto run

// Polling bit 7 of 0x4C
  for (timeout_i = 0; (timeout_i <= timeout) && (ScalerReadBit(0x4C, 7) == 0); timeout_i++)
    if (timeout != timeout_i) delay(1); // wait 1 ms
    else
    {
       Serial.println("Time-out hysnc type detection");
       return -3;
    }

  Serial.print("HSync type detection ready            => ");Serial.println(ScalerReadBit(0x4C,7),BIN);
  Serial.print("HSync type detection auto run         => ");Serial.println((ScalerReadByte(0x4C) & 0x70) >> 4,BIN);
  return(0);
}

Now some Serial monitor testing data log where the RTD2660H board will either have NO INPUT or VGA input or RGBS input disconnected live (code 110 is for VGA and code 101 is for RGBS with XOR hsync-vsync)

Code: [Select]

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 558
HSync type detection ready            => 1
HSync type detection auto run         => 110

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 559
HSync type detection ready            => 1
HSync type detection auto run         => 110

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 559
HSync type detection ready            => 1
HSync type detection auto run         => 110

ISP mode entered - DW8051 reset
No Input

ISP mode entered - DW8051 reset
No Input

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 1705
HSync type detection ready            => 1
HSync type detection auto run         => 101

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 1705
HSync type detection ready            => 1
HSync type detection auto run         => 101

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 1705
HSync type detection ready            => 1
HSync type detection auto run         => 101

ISP mode entered - DW8051 reset
No Input

ISP mode entered - DW8051 reset
No Input

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 559
HSync type detection ready            => 1
HSync type detection auto run         => 110

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 558
HSync type detection ready            => 1
HSync type detection auto run         => 110


[Tantratron]

I've found still an incomplete register/scaler initialization required to really have auto detection of VGA or RGBS.

As long as say the OpenRTD russian firmware first initialize and sense either VGA or RGBS input signal then no problem under ISP mode to then always detect either No input, RGBS input or VGA input.

However if the RD2660 board running under OpenRTD firmware was never connected to any valid input (RGBs or VGA), once entering ISP mode via I2C arduino then it is impossible to later auto detect (my previous scketch). So there must be some additional register/scaler setup to really go into a full automatic signal detection.

What i've done after checking some commands in the realtek leaked file (sync.c from KerJoe) is to display these specific register values.

No Signal

Code: [Select]

ISP mode entered - DW8051 reset
********************
Page 0: P0_ADC_POWER_C6   => 38
Common Page register 0x16 => 8
Common Page register 0x32 => 0
Common Page register 0x49 => 6
Page 0: P0_ADC_POWER_D5   => 0
********************
No Input

VGA signal

Code: [Select]

ISP mode entered - DW8051 reset
********************
Page 0: P0_ADC_POWER_C6   => 3F
Common Page register 0x16 => C
Common Page register 0x32 => 30
Common Page register 0x49 => 66
Page 0: P0_ADC_POWER_D5   => 0
********************
Signal present
Stable Hysnc period       => 558
HSync type detection auto run         => 110
VGA input

RGBs signal

Code: [Select]

ISP mode entered - DW8051 reset
********************
Page 0: P0_ADC_POWER_C6   => 3F
Common Page register 0x16 => A
Common Page register 0x32 => 23
Common Page register 0x49 => 66
Page 0: P0_ADC_POWER_D5   => 0
********************
Signal present
Stable Hysnc period       => 1705
HSync type detection auto run         => 101
RGBS input

There might be other register/scaler in need for additional parameters setup so my previous auto detect routine would always work, no idea but that is where i'm now stuck.

[avst]

There might be other register/scaler in need for additional parameters setup so my previous auto detect routine would always work, no idea but that is where i'm now stuck.

In Sync.c:

Code: [Select]

         ....
         CScalerSetBit(_SYNC_SELECT_47, ~(_BIT3 | _BIT2), (_BIT3 | _BIT2));//SOY1 ,2nd HS/VS
       
        //HS_RAW/SOY,source selection
        CScalerSetBit(_SYNC_SELECT_47, ~_BIT4, ((BYTE)bHsyncSelection << 4));
        synctypetemp    = CSyncSearchSyncTypeVGA();
        break;
        .....

BYTE CSyncGetSyncTypeStepVGA(void)
{
    BYTE flag, cnt = 0;
   
    CScalerPageSelect(_PAGE0);
    CScalerSetByte(_P0_ADC_POWER_AD, 0x18);//DCR  enable,1M
   
    CScalerSetByte(_VGIP_ODD_CTRL_13, 0x00);
    CScalerSetByte(_YUV2RGB_CTRL_9C, 0x00);//disable YUV->RGB
    CScalerSetBit(_IPH_ACT_WID_H_16, ~(_BIT7 | _BIT3), 0x00);
    CScalerSetBit(_SCALE_CTRL_32, ~_BIT7, 0x00); //disable video compensation
    CScalerSetBit(_SYNC_CTRL_49, ~(_BIT2 | _BIT1 | _BIT0), _BIT2 | _BIT1); // SeHS/DeHS ,ADC_HS/ADC/VS
    CScalerSetBit(_SYNC_INVERT_48, ~(_BIT4 | _BIT2), (_BIT4 | _BIT2));// HS_OUT ,clamp output enable
   
    if((bit)CScalerGetBit(_SYNC_SELECT_47, _BIT4)) //V304 modify
    {
        CScalerPageSelect(_PAGE0);
        CScalerSetByte(_P0_ADC_TEST_CTRL_AF, 0x04);
    }
   
    CScalerSetBit(_SYNC_SELECT_47, ~_BIT5, _BIT5);  //Enable De-composite circuit
   
    // Vsync counter level 384 crystal clocks
    CScalerSetBit(_VSYNC_COUNTER_LEVEL_MSB_4C, ~(_BIT2 | _BIT1 | _BIT0), 0x03);//768Hsync
    CScalerSetByte(_VSYNC_COUNTER_LEVEL_LSB_4D, 0x00);
   
    do
    {
        CScalerSetBit(_STABLE_MEASURE_4F, ~_BIT0, 0x00);
        CScalerSetBit(_STABLE_MEASURE_4F, ~_BIT0, _BIT0);//Measure start
        ....

Maybe this helps

[Tantratron]

Hello @avst,

The source file Sync.c from Realtek is very long, very complex or seems to cover many types of sync, many type of input signals.

So far, I was able to understand from your suggestions on january 1st how to auto-detect what type of sync signals through this part of sync.c code

Code: [Select]

#if(_HSYNC_TYPE_DETECTION == _AUTO_RUN)
/**
* CSyncGetSyncTypeAutoRun
* Get VGA sync type by Hsync Type Detection Auto Run
* @param <none>
* @return {sync type}
*
*/
BYTE CSyncGetSyncTypeAutoRun(void)
{

...............................

CScalerSetBit(_STABLE_MEASURE_4F, ~_BIT0, 0x00);//Measure- Clear
CScalerSetBit(_STABLE_MEASURE_4F, ~_BIT0, _BIT0);//Measure- Start

CTimerDelayXms(5);

if((bit)CScalerGetBit(_HSYNC_TYPE_DETECTION_FLAG_4E, _BIT7))
    {// Hsync overflow
return _NO_SYNC_STATE;
    }

//eric 20070523 VGA long time wake up
CTimerDelayXms(60);

    if(!((bit)CScalerGetBit(_STABLE_MEASURE_4F, _BIT7)))//both polarity and period are stable
        return _NO_SYNC_STATE;
CScalerSetBit(_STABLE_MEASURE_4F, ~_BIT1, _BIT1);//Pop up result

    // Get stable period
CScalerRead(_STABLE_PERIOD_H_50, 2, pData, _AUTOINC);
((WORD *)pData)[1] = ((pData[0] & 0x07) << 8) | pData[1];

...............

CScalerSetBit(_STABLE_MEASURE_4F, ~_BIT0, 0x00);//stable measure stop

CScalerSetBit(_SYNC_SELECT_47, ~_BIT6, 0x00);
CScalerSetBit(_SYNC_SELECT_47, ~_BIT6, _BIT6); //Enable hsync type detection auto run

if(CTimerPollingEventProc(90, CMiscHsyncTypeAutoRunFlagPollingEvent)) //auto run ready
{
synctemp = (CScalerGetBit(_VSYNC_COUNTER_LEVEL_MSB_4C, 0xff) & 0x70) >> 4;//Measur result

...............................

from which I made below my last code which works detecting if VGA or RGBs or NoInput

Code: [Select]

int8_t AutoDetectInput(void)
{
uint8_t timeout_i, timeout=90, type_input;

// Reset auto sync detection
  ScalerWriteBit(0x4F, 0, 0b0);
  ScalerWriteBit(0x4F, 0, 0b1);
  delay(5); // wait 5 ms

//check if Hsync is present looking at hsync counter overflow
  if(ScalerReadBit(0x4E,7))
  {
    Serial.println("No Input");
    return(-1);
  }
  else
  {
    delay(60); // wait another 60 ms
    if(ScalerReadBit(0x4F,7)==0)
    {
      Serial.println("No stable measurement");
      return(-2);
    }
    Serial.println("Signal present");
    ScalerWriteBit(0x4F, 1, 0b1); // pop up stable value
  }
  Serial.print("Stable Hysnc period       => ");Serial.println(((ScalerReadByte(0x50) & 0x7) << 8) + ScalerReadByte(0x51),DEC);
  ScalerWriteByte(0x4C, (ScalerReadByte(0x4C) & 0xF8) | (ScalerReadByte(0x50) & 0x07));
  ScalerWriteByte(0x4D,ScalerReadByte(0x51));
  ScalerWriteBit(0x4F, 0, 0b0);  // stop stable measure
  ScalerWriteBit(0x47, 6, 0b0);
  ScalerWriteBit(0x47, 6, 0b1);  // enable hysnc type detection auto run

// Polling bit 7 of 0x4C
  for (timeout_i = 0; (timeout_i <= timeout) && (ScalerReadBit(0x4C, 7) == 0); timeout_i++)
    if (timeout != timeout_i) delay(1); // wait 1 ms
    else
    {
       Serial.println("Time-out hysnc type detection");
       return -3;
    }
  type_input = (ScalerReadByte(0x4C) & 0x70) >> 4;
  Serial.print("HSync type detection auto run         => ");Serial.println(type_input,BIN);
  if(type_input == 0) Serial.println("Not support");
  if(type_input == 5) Serial.println("RGBS input");
  if(type_input == 6) Serial.println("VGA input");
  return type_input;
}

However it only works if either RGBs or VGA signal was initially detected by OpenRTD2662 firmware. If no input signal was detected, the OpenRTD2662 will wait and detect any signal with its own unknown loop. Once entering ISP mode, the DW8051 is halted so we need to generate via the arduino as a Kernel the correct detection loop which means other register programming.

[Tantratron]

OK after displaying different registers content, I might have found the issue where the russian firmware seems to random allocate bit 4 of register 0x47 when no signal is present at boot then entering ISP mode. This bit says if SOG/SOY or HS_RAW(SS/CS) input sync selection so now prior reset auto sync function, I do force this specific bit to 0. Same story with ADC RGB power which seems sometimes incomplete so I do force to power on all inputs.

So far now, below updated auto sync source file provides a self-input detection wether RGBs VGA or No input.

Code: [Select]

int8_t AutoDetectInput(void)
{
uint8_t timeout_i, timeout=90, type_input;

  ScalerWriteByte(S_PAGE_SELECT, 0);
  ScalerWriteByte(0xC6, 0x0F);     // set ADC RGB power
  ScalerWriteBit(0x47, 4, 0b0);    // choose HS_RAW(SS/CS) source selection

// Reset auto sync detection
  ScalerWriteBit(0x4F, 0, 0b0);
  ScalerWriteBit(0x4F, 0, 0b1);
  delay(5); // wait 5 ms

//check if Hsync is present looking at hsync counter overflow
  if(ScalerReadBit(0x4E,7))
  {
    Serial.println("No Input");
    return(-1);
  }
  else
  {
    delay(50); // wait another 50 ms
    if(ScalerReadBit(0x4F,7)==0)
    {
      Serial.println("No stable measurement");
      return(-2);
    }
    Serial.println("Signal present");
    ScalerWriteBit(0x4F, 1, 0b1); // pop up stable value
  }
  Serial.print("Stable Hysnc period       => ");Serial.println(((ScalerReadByte(0x50) & 0x7) << 8) + ScalerReadByte(0x51),DEC);
  ScalerWriteByte(0x4C, (ScalerReadByte(0x4C) & 0xF8) | (ScalerReadByte(0x50) & 0x07));
  ScalerWriteByte(0x4D,ScalerReadByte(0x51));
  ScalerWriteBit(0x4F, 0, 0b0);  // stop stable measure
  ScalerWriteBit(0x47, 6, 0b0);
  ScalerWriteBit(0x47, 6, 0b1);  // enable hysnc type detection auto run

// Polling bit 7 of 0x4C
  for (timeout_i = 0; (timeout_i <= timeout) && (ScalerReadBit(0x4C, 7) == 0); timeout_i++)
    if (timeout != timeout_i) delay(1); // wait 1 ms
    else
    {
       Serial.println("Time-out hysnc type detection");
       return -3;
    }
  type_input = (ScalerReadByte(0x4C) & 0x70) >> 4;
  Serial.print("HSync type detection auto run         => ");Serial.println(type_input,BIN);
  if(type_input == 0) Serial.println("Not support");
  if(type_input == 5) Serial.println("RGBS input");
  if(type_input == 6) Serial.println("VGA input");
  return type_input;
}
I will proceed with next steps suggest while ago by @avst, see below

It is clear that I need to put much more effort and focus to learn porch, APLL and DPPL modification programming

The steps these firmwares take are more or less:

• Detect the signal (activity on sync signals)
• Measure availabe data: Vtotal, Hor. frequency, Ver. frequency, sync polarity and sync width
• Lookup or calculate missing values, Htotal, Hstart and Vstart. Mostly done with a large lookup table. If there is not perfect match, take something similar
• With the Htotal value, the sampling clock can be determined to setup the source pll.
• From the values obtained, the input capture area (position and size) can be setup
• With the horizontal and vertical active, the scaling can be calculated
• From the scaling the pixel clock for the output can be calculated to setup the output pll
• Now the output interface can be setup and the LCD enabled. Note that the output timing varies depending on the input timing, and there are cases, where the output timing would be outside the LCD specs.
• Most often, the table or calculated values will not be perfect, so some fine tuning has to be done (HTotal, sampling phase and position).This is the auto adjust most firmwares offer. These differ from chip to chip, but all are image dependent, which is not 100% bulletproof. E.g. horizontal/vertical position may be deduced from the first non black pixel.
• Sometimes the ADC range can be auto adjusted, provided a suitable image is displayed.
• After everything is finished, the firmware monitors the input timing, to start the whole cycle again, if a significant change occurs

[Tantratron]

Hello again, here is a status where I'm in this project and learning path.

First I'm following teh guidelines from KERJOE in this post, in particular these different steps

Here's a rundown of the VGA setup sequence:

• Write EDID information into the memory and enable acces to it on I2C.
• Setup GPIO mode for display power, mirroring, backlight. Then set GPIO state to enable them.
• Reset and power on all scaler submodules.
• Write LCD panel timings, select TTL/LVDS mode and power up the output.
• Set the LCD panel output frequency such, that the horizontal frequency of input and output video signals match.
• Setup capture window to input resolution, setup FIFO window to either input or output resolution whichever is less.
• Setup and power up one of the analog component video channels.
• Set its sampling frequency to the pixel clock of the incomming signal.
• If you dont want the picture to overflow the screen or display only on a part of it, you need to scale up the picture. Write the filter coeficients to the scaling registers and either scale up and/or down for both width and height.

Since my actual RTD2660 board is loaded with OpenRTD2662 russian firmware, what I do systematically is boot the board without any video signal input (VGA or RGBs interlaced). For the moment, there is no need to learn or write source for steps 2, 3, 4 and 5 because it seems automatically filled wether video signal is present or not.

As for step 1, unless I'm wrong my small LCD's do not have any EDID information to be read from.

Second I've now stable arduino sketch able to comand RTD2260 to self-detect presence of any video signal, to self-detect what type of sync signal (separate Hsync and Vsync, composite sync) then if VGA or RGBs interlaced connected, to run an ANALOG measurement to estimate period of total Horizontal line, what Hsync and Vsync frequencies, polarities. See after my Serial Monitor recording of 4 cases (no input, RGBS, no input and VGA).

Code: [Select]

ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 1705
HSync type detection auto run         => 101
RGBS input

Measure in analog mode
InputMeasData.HFreq -> 15835
InputMeasData.VFreq -> 61
InputMeasData.HTotal -> 1705
InputMeasData.VTotal -> 258
InputMeasData.HSync -> 176
InputMeasData.VSync -> 0
InputMeasData.HSPolarity -> 1
InputMeasData.VSPolarity -> 1


ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 559
HSync type detection auto run         => 110
VGA input

Measure in analog mode
InputMeasData.HFreq -> 48387
InputMeasData.VFreq -> 60
InputMeasData.HTotal -> 558
InputMeasData.VTotal -> 805
InputMeasData.HSync -> 60
InputMeasData.VSync -> 800
InputMeasData.HSPolarity -> 1
InputMeasData.VSPolarity -> 0


Third I've finally understood why the measuresignal() routine of KERJOE does not work right away with DIGITAL mode, see details of the issue here. In particular why Something I need help and explanation, the only way I can get the measuresignal() routine to work is by forcing to ZERO bit 7 of register MEAS_HSYNC_PERIOD_HI otherwise it will never properly write ONE to bit 5. The reason seems that KERJOE code only worked for HDMI offering an input CLOCK whereas both with VGA or RGBs, there is no signal pixel clock.

This is why from now on in my case, I can only have good measurement in ANALOG mode with part of KERJOE source code.

Now my idea is that after all, I do know the pixel clock value inside the Advantest video section, it is 20 MHz. So I just need to understand or learn how to properly set in the RTD2660 the signal capture PLL centered around 20 MHz to track its jitter then fill correctly the input frame values after crunching the analog values.

Next will be to understand how to properly set the panel PLL clock then sync it with input PLL to match input pixel rate versus output pixel rate once rescaling is done.

If any of you knows how to help code the different registers for the input capture PLL and the output panel PLL, it would be much appreciated.

Albert

[Tantratron]

Unless i'm wrong, eventhough there seems to be some source about APLL in KERJOE project, it was not called neither tested.

So I've now just printed all the APLL register/scaler values while the RTD2660 board runs live, see after the content values for RGBS then VGA signal present so russian firmware would display successfully on the LCD

Code: [Select]

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 1705
HSync type detection auto run         => 101
RGBS input

Measure in analog mode
InputMeasData.HFreq -> 15835
InputMeasData.VFreq -> 61
InputMeasData.HTotal -> 1705
InputMeasData.VTotal -> 258
InputMeasData.HSync -> 176
InputMeasData.VSync -> 0
InputMeasData.HSPolarity -> 1
InputMeasData.VSPolarity -> 1

******** APLL values ************
register A0   = 8
register A1   = 0
register A2   = 1
register A3   = 49
register A4   = 1
register A5   = 4C
register A6   = 0
register A7   = 0
register A8   = 0
register A9   = 0
register AA   = 3
register AB   = 0
register AC   = 3
register AD   = 1
register AE   = 65
register AF   = 8
register B0   = 1
register B1   = 73
register B2   = 59
register B3   = 30
register B4   = 0
register B5   = 10
register B6   = 8
register B7   = 2
register B8   = D
register B9   = FF
register BA   = FF
register BB   = 1B
register BC   = A0
register BD   = 0
register BE   = 0
****************************************

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 558
HSync type detection auto run         => 110
VGA input

Measure in analog mode
InputMeasData.HFreq -> 48387
InputMeasData.VFreq -> 60
InputMeasData.HTotal -> 558
InputMeasData.VTotal -> 805
InputMeasData.HSync -> 60
InputMeasData.VSync -> 799
InputMeasData.HSPolarity -> 1
InputMeasData.VSPolarity -> 0

******** APLL values ************
register A0   = 8
register A1   = 0
register A2   = 14
register A3   = 1C
register A4   = 1
register A5   = 49
register A6   = 0
register A7   = 0
register A8   = 0
register A9   = 0
register AA   = 3
register AB   = 7
register AC   = 1A
register AD   = D1
register AE   = 65
register AF   = 8
register B0   = 1
register B1   = 75
register B2   = 3F
register B3   = 30
register B4   = 0
register B5   = 50
register B6   = 10
register B7   = 2
register B8   = 4D
register B9   = FF
register BA   = FF
register BB   = 1B
register BC   = A0
register BD   = 0
register BE   = 0
****************************************

Now the same APLL register reading when no input so the firmware cannot set anything correctly (no input signal) but after, i do connect respectively RGBS and VGA signal, of course I do not have any routine to setup APLL but this might help understand how the APLL is supposed to work

Code: [Select]

ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
No Input
ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 1706
HSync type detection auto run         => 101
RGBS input

Measure in analog mode
InputMeasData.HFreq -> 15835
InputMeasData.VFreq -> 61
InputMeasData.HTotal -> 1705
InputMeasData.VTotal -> 258
InputMeasData.HSync -> 176
InputMeasData.VSync -> 0
InputMeasData.HSPolarity -> 1
InputMeasData.VSPolarity -> 1

******** APLL values ************
register A0   = 4
register A1   = 47
register A2   = 0
register A3   = 18
register A4   = 0
register A5   = 0
register A6   = 0
register A7   = 0
register A8   = 0
register A9   = 0
register AA   = 0
register AB   = 7
register AC   = 9
register AD   = 20
register AE   = 63
register AF   = 9
register B0   = 0
register B1   = 45
register B2   = 2E
register B3   = 30
register B4   = 0
register B5   = 50
register B6   = 18
register B7   = 2
register B8   = C
register B9   = 0
register BA   = 0
register BB   = 1B
register BC   = A0
register BD   = 0
register BE   = 0
****************************************

ISP mode entered - DW8051 reset
Signal present
Stable Hysnc period       => 558
HSync type detection auto run         => 110
VGA input

Measure in analog mode
InputMeasData.HFreq -> 48387
InputMeasData.VFreq -> 60
InputMeasData.HTotal -> 558
InputMeasData.VTotal -> 805
InputMeasData.HSync -> 59
InputMeasData.VSync -> 799
InputMeasData.HSPolarity -> 1
InputMeasData.VSPolarity -> 0

******** APLL values ************
register A0   = 4
register A1   = 47
register A2   = 0
register A3   = 18
register A4   = 0
register A5   = 0
register A6   = 0
register A7   = 0
register A8   = 0
register A9   = 0
register AA   = 0
register AB   = 7
register AC   = 9
register AD   = 20
register AE   = 63
register AF   = 9
register B0   = 0
register B1   = 45
register B2   = 2E
register B3   = 30
register B4   = 0
register B5   = 50
register B6   = 18
register B7   = 2
register B8   = C
register B9   = 0
register BA   = 0
register BB   = 1B
register BC   = A0
register BD   = 0
register BE   = 0
****************************************


[Tantratron]

After lot of testing, reading via I2C many register.scaler contents to guess the learning road, i've been able finally to arduino run APLL wether RGBS or VGA input. There was some bug on APLL concerning the VCO_divider in KERJOE's routine

Code: [Select]

int8_t SetAPLLFrequncy(uint32_t pixelClock, uint16_t linePixelCount)
{
    // FREQUENCY_OUTPUT = FREQUENCY_INPUT * (M_VALUE + K_VALUE / 16) / N_VALUE / (1 << OUTPUT_DIVIDER)

    //       3 bit  8 bit  can be equal to 1 or 2
    uint8_t  apllN, apllM, apllDiv;
    int8_t   apllK; // 4 bit
    uint16_t apllMK; // Temporary value holding integer M and fractional K
    if (pixelClock < 5*MHZ) // TODO: Check N codes
        return;
    else if (pixelClock < 100*MHZ)
        { apllN = 3; apllDiv = 1; } // apllDiv is 1/2
    else if (pixelClock < 200*MHZ)
        { apllN = 3; apllDiv = 1; } // apllDiv is 1/2
    else
        { apllN = 3; apllDiv = 1; } // apllDiv is 1/2
which should be for pixelclock less than 100 MHz

Code: [Select]

    if (pixelClock < 5*MHZ) // TODO: Check N codes
        return 0;
    else if (pixelClock < 100*MHZ)
//        { apllN = 3; apllDiv = 1; } // apllDiv is 1/2
        { apllN = 3; apllDiv = 2; } // apllDiv is 1/2
    else if (pixelClock < 200*MHZ)
        { apllN = 3; apllDiv = 1; } // apllDiv is 1/2
    else
        { apllN = 3; apllDiv = 1; } // apllDiv is 1/2

The good news now is that I can tell APLL the real known pixel clock of 20 MHz since AVST was right in the past. The OpenRTD2662 russian firmware assumed a 13.5 MHz pixel clock for RGBs interlaced 15 KHz so it would reduce to total 858 pixels per line (standard) instead of 1264 pixels generated by my Advantest R3361 spectrum analyzer video section (not standard).

Now I need to figure out how to change frame capture parameters to store more pixel resolution, FIFO and rescaling since there is some hope to get a better video quality for my specific RGBS interlaced signal, see attached 3 pictures showing the new visual aspect.

[Tantratron]

Today major step after so much work thanks to member @avst private guidance, the source files from member @KerJoe.

For the first time, i'm able now to arduino I2C live dynamic change the russian firmware pipeline to obtain an acceptable display of the non standard RGS interlaced 15 KHz signal from my Advantest R3361 spectrum analyzer. Still lot of work to do but this is very positive after almost 3 months from scratch.

Attached picture of my 640x480 display and Kernel part in the arduino sketch commanding the RTD2660 pipeline.

Code: [Select]

// self-detects if any signal then what type of signal present on VGA lines
  type_input=AutoDetectInput();
  if(!type_input) return; 

// measure frequencies via analog mode wether VGA or RGBS
  MeasureFreqSignal();

// set input frame parameters 
  switch(type_input)
  {
    case 6:  // VGA input
      SetAPLLFrequency(65000000UL,1344);  // VGA signal 48 KHz
     
      Hact = 1024;
      Vact = 768; 

      SetCaptureWindow(179, 17, Hact, Vact, 109, 18);
      break;
    case 5:  // RGBS interlaced with Csync (XOR)
      SetAPLLFrequency(20000000UL,1264);    // IPclock 20 MHz (Advantest R3x61)
//      SetAPLLFrequency(13500000,858);       // IPclock 13,5 MHz (standard)

      Hact = 1000;
      Vact = 255;
     
      SetCaptureWindow(125, 3, Hact, Vact, 109, 17);
//      SetCaptureWindow(25, 4, Hact, Vact, 109, 17);
      break;
    default:
      Serial.println("Unknown input sync signal");
      return;
  }
 
  SetFIFOWindow(PANEL_H_ACTIVE, PANEL_V_ACTIVE);

  ScalerWriteTable(DisplayInitTable);
 
  ScaleUp(Hact, Vact, PANEL_H_ACTIVE, PANEL_V_ACTIVE);
  ScaleDown(Hact, Vact, PANEL_H_ACTIVE, PANEL_V_ACTIVE);

// Magic formula Fdisplay = (DisplayHTotal * InputHFreq) / InputVActive * DisplayVActive
  DpllFreq = (PANEL_HTOTAL * InputMeasData.HFreq) / Vact * PANEL_V_ACTIVE;
  SetDPLLFrequency(DpllFreq);


[Tantratron]

Hello, maybe after all these posts , comments, test and trial since end of last october, here is quick video I've just done showing the result (this time with LVDS display)

[pcprogrammer]

That is a good result. 

I made a small step today. Started with the FPGA and took an example program from https://github.com/sipeed/TangNano-20K-example and modified it to match my 1024*600 LCD.

To make sure that the 40 pin LCD connector has the correct pinout I verified the schematic for my version with the one of the Lichee Nano, and they do match. The only difference is that the FPC connector has the connections on the other side of the cable, so I needed to change the type A-B I use with the Lichee Nano to a type A-A. Checked the connections with continuity test on my DMM just to be sure.

The Gowin IDE I had on my system (version 1.9.8.06) did not see the Tang Nano 20K even though I could communicate with it via a cutecom terminal. It complained that the programmer software needed root permissions. Tried that, but it still did not see the Tang Nano 20K. So after some searching on the web, I found some information here: https://gist.github.com/retrofun/57b6f0bbca01f0650a8b7137f69dd674

Tried it with the version I had, but it still did not work, so I got the latest version for Linux (V1.9.11) and now I'm able to program the Tang Nano 20K.

I just gave it a try and the display shows nice color bars. The Tang Nano 20K is dangling behind the display.

Next is to setup some simulation with modelsim and think of what is needed to capture the signals generated with a STM32F411. I abandoned the Raspberry PI because it f...d up my SD card one to many times and switched to a STM32F411 because it has enough FLASH to hold all the needed raster data for a single frame and has 5 SPI peripherals of which I need 4 to make the video signals.

The second image shows a test on my big monitor of the text and grid output of the STM32F411. The monitor can't handle the signal properly. At that point the vertical settings were off, but the horizontal was correct. I used the Rigol scope to verify the timings in comparison with the captures provided by Tantratron.

[Tantratron]

Hey @pcprogrammer (Peter), you know what is crazy with the RTD2660 and the russian firmware. After I got some good results with my platform live hacking and patching through I2C arduino path the russian firmware. I thought to try the standard PCB800099-V9 board with its multi-resolution and once I took control of its firmware via my arduino sketch, it worked. So I discovered that actually the russian firmware is more or less the chinese firmware except it allows 15 KHz input with Csync but it never de-interlace. I did not learned so far how to program the RTD2660 about the de-interlacing so I did nothing which how I've discovered this new fact yesterday.

Then I took another board PCB8000196-V6 as shown in my YouTube video doing only LVDS drive, same its firmware cannot recognize my Advantest signal but once loaded with my arduino control, it worked. So I've looked on registers, nothing set on de-interlace or whatever then I've removed both scaling filters (Up and Down). Suddenly the image was very nasty, super bad then I realize that actually these scaling filters are doing an incredible job to interpolate the interlaced frames... just crazy and awesome, in fact I used the filter selected by @KerJoe from realtek's eaked files. Of course the vertical resolution is not the best but the horizontal is really good with these filters.

Code: [Select]

uint8_t coef_up[] =
{
  0x04,0x00, 0x03,0x00, 0x02,0x00, 0x00,0x00, 0xFE,0x0F, 0xFA,0x0F, 0xF6,0x0F, 0xF2,0x0F,
  0xEC,0x0F, 0xE6,0x0F, 0xE0,0x0F, 0xD9,0x0F, 0xD2,0x0F, 0xCA,0x0F, 0xC3,0x0F, 0xBB,0x0F,
  0xCA,0x0F, 0xE0,0x0F, 0xF7,0x0F, 0x13,0x00, 0x31,0x00, 0x54,0x00, 0x78,0x00, 0xA1,0x00,
  0xCB,0x00, 0xFA,0x00, 0x28,0x01, 0x5B,0x01, 0x8D,0x01, 0xC3,0x01, 0xF7,0x01, 0x2E,0x02,
  0x79,0x04, 0x72,0x04, 0x68,0x04, 0x55,0x04, 0x40,0x04, 0x25,0x04, 0x07,0x04, 0xE2,0x03,
  0xBD,0x03, 0x91,0x03, 0x65,0x03, 0x34,0x03, 0x03,0x03, 0xCE,0x02, 0x99,0x02, 0x63,0x02,
  0xB9,0x0F, 0xAB,0x0F, 0x9F,0x0F, 0x98,0x0F, 0x91,0x0F, 0x8D,0x0F, 0x8B,0x0F, 0x8B,0x0F,
  0x8C,0x0F, 0x8F,0x0F, 0x93,0x0F, 0x98,0x0F, 0x9E,0x0F, 0xA5,0x0F, 0xAD,0x0F, 0xB4,0x0F,
};

uint8_t coef_down[] =
{
  0x08,0x00, 0x09,0x00, 0x0c,0x00, 0x10,0x00, 0x15,0x00, 0x1c,0x00, 0x24,0x00, 0x2e,0x00,
  0xe9,0x00, 0x07,0x01, 0x25,0x01, 0x45,0x01, 0x64,0x01, 0x83,0x01, 0xa2,0x01, 0xbe,0x01,
  0x43,0x02, 0x3f,0x02, 0x37,0x02, 0x2a,0x02, 0x1b,0x02, 0x08,0x02, 0xf2,0x01, 0xda,0x01,
  0xcc,0x00, 0xb1,0x00, 0x98,0x00, 0x81,0x00, 0x6c,0x00, 0x59,0x00, 0x48,0x00, 0x3a,0x00,
};

Go figure out now what the russian firmware really did new because I take any other chinese board, run my sketch and it works fine. Of course, I still need to continue and make a full pipeline then see how it could be compiled with 8051, remember I do MacOS. However my point to you, probably you'll get super good result with FPGA and maybe no need of frame buffering.

This video topic is unsane, addictive and so interesting

[Tantratron]

P.S. Here is a new update showing side by side an LVDS display (6.5 inches) and RGB-6bit display (5.7 inches) with my R3361 turned on

[pcprogrammer]

As a bit of a side step from the FPGA, I was thinking about the scaling and wrote a simple test to just down sample the array with 976 active pixels to 640 pixels without any filtering, but just by stepping with a fixed point index. I used 1.525 with a 22 bit fixed point.

Code: [Select]

((1 << 22) | 2202009)
The result is not that bad, and maybe with some tweaking to use a priority on a single on pixel near the sampling point it might even prove to be all that is needed.

Edit: Changed the code to check on the pixel before the selected one and use it if one. The horizontal grid lines become less dotted and the text might be a bit bold but the result is not that bad.

[Tantratron]

As a bit of a side step from the FPGA, I was thinking about the scaling and wrote a simple test to just down sample the array with 976 active pixels to 640 pixels without any filtering, but just by stepping with a fixed point index. I used 1.525 with a 22 bit fixed point.

Could you eventually try with input active H of 1050 pixels to 640 because due to the unusual total input HxV size from Advantest (1264x525i versus 858x525i). I initially have chosen 1000 but it still eat part of right display so I've now increased to 1050, see the result now with 5.6" display.

[pcprogrammer]

Could you eventually try with input active H of 1050 pixels to 640 because due to the unusual total input HxV size from Advantest (1264x525i versus 858x525i). I initially have chosen 1000 but it still eat part of right display so I've now increased to 1050, see the result now with 5.6" display.

Sure if that is needed it is just changing the step value. But this was just as a proof of concept. In the FPGA it should be easy enough to catch what ever part of the input signal is needed.

My next objective is to get the SDRAM working to create a frame buffer for the LCD.