Raw input is 24V, which I figure to buck down to 5V as a first step before getting into the annoying shit.
1V @ 30A (PL, PS Core, BRAM).
1.8V @ 10A.
1.5V (DDR3), probably 2A or so.
0.75V (buffered divider for DDR Vtt).
Then a mess of really weird ones for MGT transceivers, must be really low noise, so probably linear regs, but current requirements for these are proving difficult to track down...
1.05V (Yes, really).
1.2V
1.8V
1.8V (Separate reg or noise filter for clock generator).
Then the non FPGA stuff,
2.7V (To be LDOd to 2.5V for some 12Gb/s reclockers).
3.3V for misc shit.
15V for a really annoying series led backlight on a front panel.
I guess 1.5, 1.3, 2, 2.7, 3.4 would be reasonable (all these are semi low current rails), getting the butch 1V and 1.8V as well would be a bonus, but I think those are going to wind up being some sort of polyphase thing probably from TI, Empirion, or AD (Who have managed to fuck up Linears web site in remarkably short order, grumble).
I know roughly what I need, it is filtering down the ways to get there that is causing me a headache.