Troubleshooting weird class D amplifier from PowerPhysics Inc.

[Yansi]

Hello,

I have got my hands on a bunch of amplifiers used in active PA speakers. They are 500 W modules made by POWERPhysics company, that unfortunately is no longer operating, so obtaining any documentation or support ain't happening. These are also about 20 years old modules, so...

The module part number seems to be PowerPhysics A-404R6.

I would like to reuse the leftover modules in other projects, so got curious how to get these running. My google-fu came up with a module datasheet and a pinout, but nothing else. Providing the voltages does unfortunately not start the module, I am getting a PROTECT output signal active and gatedriver disabled. Without any official support, I did what anyone else would do - reverse engineer the schematic. Please also see attached.

There are two pages worth of entangled bolognese, please pardon my hand drawings, I may clean it up later if that much necessary. One page is the amplifier section, which does correspond extremely well with U.S. Patent No. 6084450 (click to open), FIG. 16.  It is mostly the same, except CMP1 has swapped inputs, which I think is actually a mistake in the Fig.16 patent drawing. (it would not work as drawn imho).

The second page is full of LM339 comparators, creating entangled mess of protections and state indicators and that is where the trouble is hiding.

Note please, that VP1 and VP2 nodes as marked on multiple locations in the schematic, are the outpus of the halfbridge 1 and 2, direct from the mosfets, before the LC lowpass.

I have found, that the problem lies in U6, the window comparator (pins 1,6,7 and 2,4,5). The window thresholds are set to 1.67V and 3.33V (verified by measurement). The input for comparison, comes from a voltage divider R45-R46 (2x 105Kohm), looking at the average voltage between VP1 and VP2, with R47 (26k7) to ground and voltage smoothed by C53. See here redrawn section:



What the F! somebody wanted to achieve here? The circuit simply expects the VP1 VP2 nodes average voltage to be from 5 to 15V (three times thresholds). Why the hell would there be such a voltage? Especially, when at start, gate drivers are disabled and VP1, Vp2 are floating completely, only with stray voltages imposed there by other feedback or measurement circuitry, that also interfaces to VP1 Vp2 directly.

Of course, when the expected voltage level is not met, the latch circuit comprised of Q16, Q17 (bit below the U7 comparators on the second paper) is activated, forcing the amplifier into PROTECT state and gatedriver disabled by Q2 just above Q16, Q17.

I simply can't wrap my head around the purpose of this window comparator, as it makes absolutely zero sense, period.  As the amplifier is normally supplied B+ of 75V, running no signal idle, the VP1 and VP2 average voltage would be about half that, 37.5V, bringing about 12.5V at R47, which is obviously more, than the supply voltage of U7.

When i de-solder out the Q10 (at the comparator outputs), this damn comparators stops pulling the panic line down and the amplifier just starts working normally.

As I've said - can't understand what the hell is that comparators intention and how it is supposed to work. Hell, it must have worked somehow before, I have taken apart a production piece. I still think I have drawn the schematic correctly, expected voltages from schematic correlates well with measurement.

I have even the original matching power supplys for the amplifier modules. Have not tried with them, not brave enough shoving them in the wall socket, yet 

Also, I have notices many more weird nonsense in the design, but I do not want to make this post extra long, nobody would read it. But the other nonsense is not at least preventing the amplifier from working.

Many thanks for any ideas with those comparators.

//EDIT: Added photo of the module.

[holko]

I believe the window comparator, frequency dependent loop-gain and propagation delay in the signal path forms a self-oscillating 1-bit delta sigma modulator or a hysteresis modulator.
Looks like R49 is there mostly to compensate for input offset @ U7.

Have a look at https://www.hypex.nl/media/fe/01/90/1682341944/A%20universal%20grammar%20of%20class%20D.pdf and https://www.researchgate.net/publication/268383069_Simple_Self-Oscillating_Class_D_Amplifier_with_Full_Output_Filter_Control/link/55252a0c0cf2b123c51793be/download?_tp=eyJjb250ZXh0Ijp7ImZpcnN0UGFnZSI6InB1YmxpY2F0aW9uIiwicGFnZSI6InB1YmxpY2F0aW9uIn19


EDIT:
I obviously misread your hole post and also went way off board with my hypothesis..
Now It looks more "latch-up" or DC-detector..

EDIT...again..

A good night of sleep did the trick for me and I believe I understand the circuit a bit more clearly now;
I wager that this is indeed some sort of latch-up and DC-detector. When the high-side of VP1 is on, voltages flows through R45 and C53 starts to charge up based the time constant of it's value and R47, followed by some dead-time and now low-side on VP2 kicks in. This discharges C53 based on the same time constant through R46.

So if one of the transistors in VP1 and VP2 dies, C53 wont be discharged in the opposite cycle and the voltage across C53 will reach the reference threshold that kicks of U7.
If DC or low frequency AC is induced or somehow applied the same happens.
I guess that VP1 and VP2 should switch more or less the same on and off, if any fault or condition disturbs this so that one pair is on longer than the other one is off over a period based on the time constant formed by C53 and R46. Voltage across C53 will after a while reach the threshold voltage that trips U7.

[Yansi]

Yes, that is I think correct. Need to measure the capacitance of the C53, no idea, but guessing a rather low value. (~1nF)

But what I do not get, how the circuit should operate, as it seems failing, right at the beginning when you apply supply voltage, the Q16 Q17 latch gets triggered right away by this window comparator and the latch does not reset via the low pulse out of Q8 Q19 (a circuit produces about 500ms low pulse, after applying the gatedrive voltage - as observed by U7 comparator pins 2, 4, 5).

[Yansi]

I have eaten the bowl of bolognese and un-entangled it for better clarity.  Left is the undervoltage comparator, keeping an eye on the gatedriver supply voltage. Then there is a schmitt trigger / monostable, creating about 500ms low pulse on any positive edge of the comparators output. Presumably to reset the following circuits.

The rest of it is I think kind of self-explanatory: Any U6 comparator or U9 via D9 can trigger the latch, disabling the gatedriver (the whole amplifier). Latch is reset by opening Q15, cutting the current through the latch. So, to reset the latched shutdown, a power cycle is needed to generate a new reset pulse.

Until here all makes perfect sense.

Q10 is kind of a puzzling element, as it seems somebody wanted to disable the left-most-side U6 comparators, during the reset pulse. However, he failed miserably, as when any of the left-most-side U6 comparators has its open-collector output switched to -5V,  current through the latch can not be cut, as opening Q15 just means latch current will flow through Q10 BE junction and to any of the comparators output to -5V.

Is that a problem? I don't know. The amp must have been somehow working before. But from the circuit it is clear, that the two comparators, shown in the original post, are causing the trouble.  Why would one check for stray voltage present on the outputs of a half bridge during start-up of the amplifier? No idea.

Considering other dumb things found in the design, like a comparator with one of its outputs floating in thin air, I am not surprised, that POWERPhysics Inc. has since gone belly up. I swear, I've tried multiple times to find a connection to that pin, but there's none, just unpopulated missing components, that would set the threshold the expected way. (See U7 comparator pins 1, 6, 7 - non-inverting input just goes to the D16, all three resistors there are not populated on the PCB). 

[ajb]

I simply can't wrap my head around the purpose of this window comparator, as it makes absolutely zero sense, period.  As the amplifier is normally supplied B+ of 75V, running no signal idle, the VP1 and VP2 average voltage would be about half that, 37.5V, bringing about 12.5V at R47, which is obviously more, than the supply voltage of U7.

That's assuming that the two half bridges always have opposite polarity.  I'm not real familiar with class-D amplifier modulation/drive strategies, but that's usually not the most efficient way to operate the power stage.  When you switch the bridge from +75V to -75V, power flow initially reverses, because of the load inductance -- so after you spend some time driving energy into the load, now you're dragging that energy back out and returning it to the power supply.  Unless you want to reduce the output current as quickly as possible, it's more efficient to close both bottom (or top) switches, so the load current takes longer to decay, and you won't have to drive as much energy back into the load during the next output pulse.  It also means you only have to switch one half-bridge at a time, and can think of the output modulation in terms of positive and negative pulses that steer the output current in the desired direction.  Obviously the load current is expected to change continuously, because this is audio, but there will be times when it is fairly constant relative to the modulation frequency depending on frequency content. 

If you assume that one side of the bridge is always low, and the other side operates at a 50% duty cycle, you end up with an average of 18.75V at R47.  That makes a lot more sense for the threshold values at the window comp, and seems to sort of line up with 500W @ 4R load.  Depending on the time constant with C53, you could use this circuit to detect overdriving as well as a shorted switch in the bridge.  As to how this is supposed to work without tripping at startup, perhaps some of that other monitoring circuitry connected to VP1/VP2 is expected to pull those nodes to ~7V or something when the bridge is disabled to keep the window comp from tripping, and there's a problem with that circuitry?  Or is there any sign that the missing components were removed rather than never populated, perhaps by someone who was previously trying to fix these things?

[Yansi]

No, the topology has only two state modulation, hence why I have linked the patent. The bridge always has switched on one or the other diagonal.  So indeed at idle, both sides are at 50% PWM, with the voltage averaging to B+/2 = 75/2 = 37.5V. After going through the divider, should end up at about 12.5V or what.

Hence my headache understanding the comparator circuit. Makes zero sense and it does not work.

The bridge is driven by HIP4080 driver chip, which does not allow any other switching states anyway, apart from all being disabled completely (all outputs low).

See also FIG 14. on page 15 of the patent https://patentimages.storage.googleapis.com/0a/64/07/7caad8af3b0678/US6084450.pdf
The amplifier is actually built according to FIG 16, but that one does not show the power stage attachment to the R-S flip-flop.

Tomorrow, I will try to power up the module with the original power supply, but I don't get it what should be different that way.

[Yansi]

Plot thickens. Have just disassembled a working speaker, got the class D amp out of it and... guess what: Same components on PCB as far as I can tell.

Still haven't managed to power it up from the original PSU, will do likely tomorrow. And try taking some measurements, as to see whats happening inside the circuit.

[youngda9]

Sometimes a circuit is designed in with good intentions, and later discovered that it isn't needed or going to work as expected.  Instead of re-designing or making board modifications (adding jumper wires) to bypass, it can just be set up to stay in a state that is benign to the system.

[Yansi]

Sure, but this design screams a bit of amateur hour at places. 

Meanwhile have done a bit of scope probing on the board and figured it out.

Seems, the original module was repaired by resoldering Q10 ( ), now the module starts. Second module started right away just fine. So, not really sure, what was wrong with the first one, apart that I have removed Q10 and later returned it back.

I have also figured out the whole startup sequence, it is as following:

Applying the +15V rail triggers a possitive edge on the output of UVLO comparator. That triggers about a 500ms-1s low pulse on the output of the monostable flip flop. The negative pulse is output on the drain of Q8. Q15 is being turned off and the reset process of the Q16-Q17 latch begins.

The window comparator U6 (left side, outputs pins 1 and 2) is monitoring the average voltage at the VP1 and VP2 nodes (halfbridge outputs). Once +15V rail applied, voltage here starts rising, due to current leaking through the gate driver IC.. Once the voltage at C54 is within the threshold window of 1.66 to 3.33V, the output of the comparators goes open circuit (open collector switch turned off inside). That way, the remaining current through the Q16-17 latch via Q10 B-E junction goes to zero - latch is reset. This happens within a few milliseconds.

After the low reset pulse ends and drain of Q8 goes high, Q15 turns on, shorting base of Q10 to ground, preventing the window comparator from triggering the latch. As the reset pulse ends, gatedriver disable signal goes low (Q2 turns off).

Once the halfbridges start switching, voltage developed on C54 at the input of the window comparator raises way outside the top threshold (above 3.33V), but the window comparator can not trigger the latch any more, due to turned off Q10, with the base at -5V, held by Q15.

Howgh.


So, I understand now how it works, but don't understand the dumb idea, of checking stray voltage on halfbridge outputs, created by currents leaking through disabled gatedriver IC and mosfets.