Electronics > Projects, Designs, and Technical Stuff
Potential DIY Oscilloscope project, screen refresh rate?
Boscoe:
Hi all,
I'm tempted by a DIY oscilloscope project as I'm enjoy high speed data, analogue circuits and Verilog (and I want a good affordable rackmount scope). I've been searching for existing scope projects and found a few but none completed because, I assume, they are difficult. I want to do a single channel USB scope at 1GHz. The way I see it, is a scope could be quite easy (relative to an off the shelf product) to design and make as long as you're happy with sending images of the waveform over the USB. My question from this post is asking is this enough compared to sending all of the data to the PC? 1GB/s of data is a lot and way too much for a human to comprehend. We could do some waveform overlaying in those images to get a higher psuedo refresh rate, again done in the FPGA. Perhaps sending multiple arrays and letting the PC print as many as possible to the screen could also be an option. Ethernet could also be a nice option on FPGAs.
Just trying to get some understanding of the requirements before I attempt something like this.
PS. Does anyone have references or schematics to existing analogue front end designs?
Thanks
David Hess:
--- Quote from: Boscoe on April 21, 2019, 09:31:47 am ---My question from this post is asking is this enough compared to sending all of the data to the PC? 1GB/s of data is a lot and way too much for a human to comprehend. We could do some waveform overlaying in those images to get a higher psuedo refresh rate, again done in the FPGA. Perhaps sending multiple arrays and letting the PC print as many as possible to the screen could also be an option.
--- End quote ---
I have a similar project going but more as a stand alone instrument and what you suggest is exactly what I am pursuing but for a different reasons. DPOs (digital phosphor oscilloscopes) achieved very high waveform acquisition rates by accumulating a histogram in real time and displaying it at the screen refresh rate. If it is done correctly, then the histogram faithfully represents the statistical contents of the input. I am more interested in minimum blind time and maintaining the maximum sample rate under all conditions.
The alternative, which most DSOs use, is to capture into a long sample record (megabytes these days) and generate the display record in post processing which has the advantages of retaining the original acquisition for further processing and leveraging the high performance available in commodity CPUs without custom hardware.
The histogram method is more suitable for USB instrumentation because there is no way USB can keep up with high sample rates.
Both methods could be done simultaneously. With USB, the hardware generated histogram could be displayed in real time and the original acquisition made available as needed.
--- Quote ---PS. Does anyone have references or schematics to existing analogue front end designs?
--- End quote ---
Tektronix and HP oscilloscopes designed before about 1990 are fully documented and their service manuals are a treasure trove of circuit design information.
The Tektronix Circuit Concepts books have a lot of what you need. Check out Vertical Amplifier Circuits especially.
Chapter 7 of The Art and Science of Analog Circuit Design by Jim Williams, Signal Conditioning in Oscilloscopes and the Spirit of Invention by Steve Roach, may be the most recent discussion about what you are asking about although it deals with the high impedance side which is only applicable up to about 500 MHz. If you want 1 GHz of bandwidth, then low impedance circuit design is required.
Chapter 14 of Analog Circuit Design, Art, Science, and Personalities by Jim Williams, Good Engineering and Fast Vertical Amplifiers by John Addis, will be helpful if you want such high bandwidths and is more applicable to low impedance high bandwidth circuits.
rhb:
FWIW I am engaged in a 2-3 year effort to write a FOSS DSO FW stack for Zynq and Cyclone V based COTS DSOs. Intent is to just replace the crappy FW on COTS instruments. However, it will be readily usable on a custom design.
While progress seems almost glacial, in fact I'm making significant headway. But there is a lot of infrastructure to develop. In addition, my background is oil exploration seismic which while a lot more sophisticated than what the EE community does, it quite different. Seismic can take a week to process 10 TB of data on 20-30,000 CPU cores. That is not practical for EE applications of DSP.
Historically the AFE of a scope is a major problem. Tek kept the design equations as a trade secret for many years. IThe big issue is component heating on a fast step. Front end alignment of a fast scope is a long, iterative process.
I strongly recommend reading the service manuals for the Tek 465, 475 and 485. They explain every circuit segment in the instrument in exquisite detail and are an absolute joy to read. Tek at its best.
David is absolutely correct that the way to handle the data is to construct a histogram in XY and then sample that at 60 Hz for the display.
Persistence, presenting the histogram of the last N sweeps is hard. I still don't know how to do that without requiring excessive resources.
Component tolerance spread in the AFE is best handled by a DSP filter in the FPGA.
Boscoe:
--- Quote from: David Hess on April 21, 2019, 06:22:32 pm ---
--- Quote from: Boscoe on April 21, 2019, 09:31:47 am ---My question from this post is asking is this enough compared to sending all of the data to the PC? 1GB/s of data is a lot and way too much for a human to comprehend. We could do some waveform overlaying in those images to get a higher psuedo refresh rate, again done in the FPGA. Perhaps sending multiple arrays and letting the PC print as many as possible to the screen could also be an option.
--- End quote ---
I have a similar project going but more as a stand alone instrument and what you suggest is exactly what I am pursuing but for a different reasons. DPOs (digital phosphor oscilloscopes) achieved very high waveform acquisition rates by accumulating a histogram in real time and displaying it at the screen refresh rate. If it is done correctly, then the histogram faithfully represents the statistical contents of the input. I am more interested in minimum blind time and maintaining the maximum sample rate under all conditions.
The alternative, which most DSOs use, is to capture into a long sample record (megabytes these days) and generate the display record in post processing which has the advantages of retaining the original acquisition for further processing and leveraging the high performance available in commodity CPUs without custom hardware.
The histogram method is more suitable for USB instrumentation because there is no way USB can keep up with high sample rates.
Both methods could be done simultaneously. With USB, the hardware generated histogram could be displayed in real time and the original acquisition made available as needed.
--- Quote ---PS. Does anyone have references or schematics to existing analogue front end designs?
--- End quote ---
Tektronix and HP oscilloscopes designed before about 1990 are fully documented and their service manuals are a treasure trove of circuit design information.
The Tektronix Circuit Concepts books have a lot of what you need. Check out Vertical Amplifier Circuits especially.
Chapter 7 of The Art and Science of Analog Circuit Design by Jim Williams, Signal Conditioning in Oscilloscopes and the Spirit of Invention by Steve Roach, may be the most recent discussion about what you are asking about although it deals with the high impedance side which is only applicable up to about 500 MHz. If you want 1 GHz of bandwidth, then low impedance circuit design is required.
Chapter 14 of Analog Circuit Design, Art, Science, and Personalities by Jim Williams, Good Engineering and Fast Vertical Amplifiers by John Addis, will be helpful if you want such high bandwidths and is more applicable to low impedance high bandwidth circuits.
--- End quote ---
I'm curious, what are you reasons for making one?
I like the idea of the histogram, this makes sense. I'm going to do some reading about this.
Just found a pdf of The Art and Science of Analog Circuit Design, I like the style it's written in. That is a great chapter, just read through it. Hardcore analogue electronics! I seriously need to brush up. I feel so many electronic engineers know their way around a microcontroller but analogue electronics is the real deal!
I'll add Good Engineering and Fast Vertical Amplifiers to my reading list, too.
I will clarify I'm looking for a 1GHz sample rate so 300MHz of bandwidth would be about right.
I would love a method to implement a front ens with opamps but the real killer is the voltage and noise performance, bandwidth is not easy there either. I think I might cheat and restrict the input range to something like +/-100V. I think that would cover the vast majority of my projects.
Boscoe:
--- Quote from: rhb on April 21, 2019, 06:58:42 pm ---FWIW I am engaged in a 2-3 year effort to write a FOSS DSO FW stack for Zynq and Cyclone V based COTS DSOs. Intent is to just replace the crappy FW on COTS instruments. However, it will be readily usable on a custom design.
While progress seems almost glacial, in fact I'm making significant headway. But there is a lot of infrastructure to develop. In addition, my background is oil exploration seismic which while a lot more sophisticated than what the EE community does, it quite different. Seismic can take a week to process 10 TB of data on 20-30,000 CPU cores. That is not practical for EE applications of DSP.
Historically the AFE of a scope is a major problem. Tek kept the design equations as a trade secret for many years. IThe big issue is component heating on a fast step. Front end alignment of a fast scope is a long, iterative process.
I strongly recommend reading the service manuals for the Tek 465, 475 and 485. They explain every circuit segment in the instrument in exquisite detail and are an absolute joy to read. Tek at its best.
David is absolutely correct that the way to handle the data is to construct a histogram in XY and then sample that at 60 Hz for the display.
Persistence, presenting the histogram of the last N sweeps is hard. I still don't know how to do that without requiring excessive resources.
Component tolerance spread in the AFE is best handled by a DSP filter in the FPGA.
--- End quote ---
Sorry, I have been in electronics for 10 years and have no idea what FOSS and COTS is. English please!
Congratulations on your progress, the project sounds very interesting. It always makes sense to do it properly once. If others can benefit, that's fantastic.
I am finding the AFE the hardest part, I will check out your suggestions, thank you.
I think I will collate my findings and create some kind of reference on my website. I think a scope AFE standard schematic could be very useful and portable.
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