power decoupling myths

[electrolust]

https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values (2020)
https://ewh.ieee.org/r3/enc/emcs/archive/2012-10-10b_DecouplingMyths.pdf (2012)

[Bud]

The best approach is to always do your own analysis

The best approach is to hook up a spectrum analyzer to the first revision board and adjust the capacitors values for best noise supression within the range of frequencies of interest. Any other aporoach you will be shooting in the dark.

[Tomorokoshi]

That is similar to the Hoffman Effect!

https://conradhoffman.com/hoffman_effect.htm

[David Hess]

I would be more impressed if some empirical designs which failed that analysis were included, with an analysis of why they failed.

I had nearly perfect application to make a test case for three different values versus three of the same value.  Initially 12 surface mount capacitors of the same large value were placed in parallel *in a radially symmetrical transmission line structure*, and it completely failed up to 1.2 GHz.  Replacing the capacitors with a set using three decades of values worked from 50 MHz to 1.2 GHz.

The only reason I even initially tried the 12 larger value capacitors was because in theory, as given in the examples above, it should have worked, but I was skeptical enough to have also ordered additional capacitors to make a decade set which ended up saving me considerable time.

[CatalinaWOW]

I object to this use of of the word, myths, which is found widely in Facebook clickbait.

The articles are completely correct, new packaging techniques have changed the rules for design, but the old rules were not anti-factual.  Just limited applicability.

It is like calling turn of the twentieth century engineering handbooks myths because they have tables of strength of various wood species that cannot be duplicated today.  The tables were correct for the old growth wood being used almost totally at the time.  They don't apply to wood grown in rapid growth tree farms which constitute much of the wood on the market today.

Engineers in all fields have to understand what they are doing.  If they don't they are really technicians.  Or amateurs.

[David Hess]

Engineers in all fields have to understand what they are doing.  If they don't they are really technicians.  Or amateurs.

That brings up something I almost included in my post.  Schematics which show multiple different values of decoupling capacitor in parallel assume a context where the reader understands what the objective is, just like there is a context for how the layout should be done with separate return current paths despite how the parts are shown connected together.

The articles are completely correct, new packaging techniques have changed the rules for design, but the old rules were not anti-factual.  Just limited applicability.

Newton's law of gravitation is another example.  It is demonstrably wrong, but completely adequate in most applications, with GPS being one of the few exceptions.

If I am laying out a modern surface mount board with power and ground planes, then I would not expect to use decoupling rules intended for through hole parts on a two sided board.  On the other hand, my ideal test using a radially symmetrical transmission line makes me question modern rules; something is missing.

[vk6zgo]

I object to this use of of the word, myths, which is found widely in Facebook clickbait.

The articles are completely correct, new packaging techniques have changed the rules for design, but the old rules were not anti-factual.  Just limited applicability.

It is like calling turn of the twentieth century engineering handbooks myths because they have tables of strength of various wood species that cannot be duplicated today.  The tables were correct for the old growth wood being used almost totally at the time.  They don't apply to wood grown in rapid growth tree farms which constitute much of the wood on the market today.

Engineers in all fields have to understand what they are doing.  If they don't they are really technicians.  Or amateurs.

Is that why technicians & amateurs spend a lot of their time fixing engineers' stuff ups?

[Siwastaja]

The mistake people make is they think the capacitors provide low impedance to the load by working at the operating point of minimum possible impedance, that defined by ESR only, i.e., at the SRF.

Of course, loads that only require low supply impedance at one very specific frequency can theoretically exist - a sine wave oscillator could be a theoretical example, but I don't know if they can be realistically built that way -, but even then, tuning the capacitor SRF to happen exactly at that frequency despite component variations, would be next to impossible.

Some resonant power converter design could utilize the low impedance point of a capacitor and auto-tune to it, but especially in this case you would want to have one strong resonant frequency, not a combination of many.

Real loads, bypassing ICs for example, tend to require low supply impedance over a broad area of frequencies. Zero impedance from DC to infinity would be nice, our target.

If the switching load pulls square-ish current pulses that contain significant energy from 1MHz to 100MHz, what good does it do if we have a nice capacitor that can supply current at low impedance at 40.1234MHz? No, we need it to give good enough impedance over the whole frequency area. And when this is the case, having a high-Q, narrow band of being "better than good enough", can only increase the risk of unexpected oscillations.

So this shows that already, the SRF dip in single capacitor solution is already an unwanted side effect.

Now, adding multiple different capacitors in parallel makes multiple dips in the impedance plot because of their different SRF.

The claim often seen is, now these different SRF dips somehow combine to give low overall impedance. This is obviously false; combining low-ESR (high-Q) ceramics cause combination of multiple narrow dips, with massive holes in-between.

So this offers no benefit because we didn't need that SRF dip to begin with; it's still just a collection of narrow frequencies that still form a very small percentage of the needed bandwidth. You still need to utilize the impedance between these dips to provide the load the impedance it needs.

In which case, using one large capacitor which has the lowest overall impedance is the obvious, and right solution.

Multi-capacitor solution becomes interesting, even theoretically, only when the large capacitor alone has too much inductance. Paralleling 1nF, 10nF, 100nF ceramic capacitors on a 3.3V supply makes absolutely no sense since 100nF is available in the smallest packages, with the same inductance as 1nF.

[OwO]

I had nearly perfect application to make a test case for three different values versus three of the same value.  Initially 12 surface mount capacitors of the same large value were placed in parallel *in a radially symmetrical transmission line structure*, and it completely failed up to 1.2 GHz.  Replacing the capacitors with a set using three decades of values worked from 50 MHz to 1.2 GHz.

That is very strange, because in my experience it's very hard to fuck up decoupling below 3GHz. Even just one or two capacitors of 470nF or 1uF gives low impedance up to 6GHz without any effort. If you are having problems at 1.2GHz the layout must be at fault.

IMO the layout is as important as the capacitors themselves, especially where you put ground vias. I drew a quick illustration of the problem:


The blue lines show current paths:


Or even worse, using a single ground via for a decoupling cap.
Btw the layout shown on the left performs better than putting vias inside the pads. You can avoid via-in-pad completely if you know what you are doing, even at many GHz.

[OwO]

This is how you do it for a 0402 cap:

[Ice-Tea]

What's the target application/frequency for that layout? Seems a bit overkill for a 'regular' board. Not to mention that it will be a total pain for other layers. If you do that for every cap on the board, power planes are going to look like a horror show...

[OwO]

Don't use power planes (unless the situation really calls for it, and never as a rule of thumb). That's another myth. This is a 4 layer board and the frequency range is 6GHz. On 4 layers with this stackup (0.2mm prepreg), power planes are completely useless for decoupling. The only potential use case for a power plane is to serve a double purpose of a ground plane that signals can travel against and at the same time deliver power. That's what I did for DDR3 + Zynq on 4 layers, but it's not going to work for RF applications because you'd need a stitching capacitor ever few mm.

[Ice-Tea]

Interesting. I was under the impression powerplane/gndplane capacitive coupling was the highest freq/"first line responder". Granted, probably works better if the separation is less than 0.2mm but still.. Any documentation for that?

[T3sl4co1l]

Don't use power planes (unless the situation really calls for it, and never as a rule of thumb). That's another myth. This is a 4 layer board and the frequency range is 6GHz. On 4 layers with this stackup (0.2mm prepreg), power planes are completely useless for decoupling. The only potential use case for a power plane is to serve a double purpose of a ground plane that signals can travel against and at the same time deliver power. That's what I did for DDR3 + Zynq on 4 layers, but it's not going to work for RF applications because you'd need a stitching capacitor ever few mm.

RF applications differ as greatly as any other application does.  Approval or dismissal of planes is irrelevant without additional facts.

You wouldn't route RF signals through planes themselves, that's ridiculous.  But then, what about the very wide stripline connections to large power transistors?  These have line-wave transmission line impedances of a few ohms -- they would be excellent planes for a DDR interface!

Conversely, you would route RF signals over power planes, even gaps between planes.  The gaps can be bypassed locally as needed, or differential signals can be used.  (Preferably, gaps are avoided, of course.)

That is similar to the Hoffman Effect!

https://conradhoffman.com/hoffman_effect.htm

Not a very solidly stated thesis, but the result is equivalent I think to noting that, for a C1 || (R+C2) network, R = Xc1 and C2 > 2.5 C1 should be chosen to thoroughly spoil the Q of C1 at the crossover frequency (which is also what gives Xc1).

Tim
Tim

[TheUnnamedNewbie]

Ever since I put a number of layouts into actual EM solvers I realized that everyone on the internet who says 'you have to do it this way' is wrong.

The way you have your grounds, and your substrate thickness, and whether or not you cannot have blind vias, all matter and completely change what is the 'best approach'. Not to mention that people often confuse two completely different ideas and don't get that they are two different targets with different ways to get there.
If you really want to understand and know, do yourself a favor: Stop going by some online forum post telling you what to do, and go rent/buy a copy of an EM package for a few weeks, and actually play around in that. Try different substrates, different thicknesses, different types of capacitor, different styles of mounting, etc. Notice how sometimes, it's actually better to just wire to the chip than to try and drop down to a via on a plane, because that added loop area is doing more harm than good. Or that trying to get 10 mOhm supply impedance at 100 MHz is pretty much pointless, because a single bondwire will absolutely destroy your impedance at that frequency.

Sometimes your traget is noise suppression/noise isolation. You want noise from device A not to get to device B. In part by making the power supply able to counter some of the noise, in part by throwing filter caps at it, and in part by reducing the noise in the first place with more capacitance. Applications? LNAs, precision analog, etc.

But other times your target isn't noise suppression, but is actually supply impedance. Getting high performance, high power RF amplifiers and so on to work, often has far less to do with keeping noise in the PA at bay, and much more to do with making sure the PA can draw whatever current it damn well pleases without the supply limiting that.

Some interesting things I found: When working with 2/4 layer PCBs, going to ground plane near chip was pointless, because the via inductance negated any benefit. But on some of the very high frequency boards I'm working, with 50um core's, using blind vias, going to planes actually made my 0402 caps completely unnecessary.

There are also some interesting things when putting caps in parallel - Dell has a patent (US 6,337,798) that claims that putting caps in parallel will actually significantly reduce the efficacy of those caps because of skin effect and current crowding.

This is also why I suspect that OwO's example is actually not useful. The current crowding will just make all but the few outer vias pointless. Might as well get rid of them, your routing, and your wallet will thank you.

I have a bunch of slides that I've been meaning to release about this, but right now they still contain a bunch of unpublished PCBs as examples so I have to wait a few more months before I can.

Another thing I learned: Discrete components are pointless to do any decoupling past a few hundred MHz. Even if you ignore any layout effects, the interal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range. You just can't get around that without using special bonded capacitors meant for RF/MMIC applications. And to be frank, even if you could, your bond wires will just ruin that too. Just trust that the IC guys know their stuff and take care of decap past 100 MHz.

[ehughes]

Ever since I put a number of layouts into actual EM solvers I realized that everyone on the internet who says 'you have to do it this way' is wrong.

What field solver do you use?

[SiliconWizard]

I object to this use of of the word, myths, which is found widely in Facebook clickbait.

The articles are completely correct, new packaging techniques have changed the rules for design, but the old rules were not anti-factual.  Just limited applicability.

It is like calling turn of the twentieth century engineering handbooks myths because they have tables of strength of various wood species that cannot be duplicated today.  The tables were correct for the old growth wood being used almost totally at the time.  They don't apply to wood grown in rapid growth tree farms which constitute much of the wood on the market today.

Engineers in all fields have to understand what they are doing.  If they don't they are really technicians.  Or amateurs.

Yup. Obviously rules that made sense when using TH capacitors are not to be translated directly when using modern SMD packages.
Still, they have the merit of making engineers AWARE of the question of frequency response for capacitors. May sound obvious for experienced engineers, but still not so much for beginners; and this kind of articles, along with the fact things have indeed evolved a lot with modern packaging, doesn't necessarily help: sure this is food for thought for the experienced, but may give a false impression for young engineers that capacitors' frequency response doesn't matter at all. And yes, beyond caps, PCB design can matter a lot too.

You may object that you don't have inexperienced engineers design high-frequency stuff anyway, but reality is sometimes a different story. When dealing with digital circuits these days, a given design has a good chance of being in the high-frequency realm.

[TheUnnamedNewbie]

Ever since I put a number of layouts into actual EM solvers I realized that everyone on the internet who says 'you have to do it this way' is wrong.

What field solver do you use?

Keysight ADS/Momentum and EMPro/HFSS for 3D simulations. I realize that those tools are outside of the average engineers budget, but you can also get very capable simulators like Sonnet and similar for lower cost, especially if you just want to do smaller simulations (like, say, some individual decoupling capacitors).

[David Hess]

I had nearly perfect application to make a test case for three different values versus three of the same value.  Initially 12 surface mount capacitors of the same large value were placed in parallel *in a radially symmetrical transmission line structure*, and it completely failed up to 1.2 GHz.  Replacing the capacitors with a set using three decades of values worked from 50 MHz to 1.2 GHz.

That is very strange, because in my experience it's very hard to fuck up decoupling below 3GHz. Even just one or two capacitors of 470nF or 1uF gives low impedance up to 6GHz without any effort. If you are having problems at 1.2GHz the layout must be at fault.

The problem was that the layout was much better than anything possible on a board; the capacitors were literally and physically part of a coaxial transmission line, and everything was symmetrical.  So there wasn't anything to adjust or improve except maybe fabrication accuracy.

A similar coplanar waveguide would have been limited to 4 capacitors and I was up against power limits so the radial structure was used instead allowing 12, or even more had I made it larger, capacitors in parallel.  And if it was a large signal effect from high power, then why would the lower value capacitors improve the situation?

Lacking suitable RF test equipment, I declared victory and moved on.  Had it not worked, I would have replaced the common C0G ceramic capacitors with RF capacitors and tried again.

[OwO]

Another thing I learned: Discrete components are pointless to do any decoupling past a few hundred MHz. Even if you ignore any layout effects, the interal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range. You just can't get around that without using special bonded capacitors meant for RF/MMIC applications. And to be frank, even if you could, your bond wires will just ruin that too. Just trust that the IC guys know their stuff and take care of decap past 100 MHz.

Or actually you know, make real life measurements that will tell you a typical 0402 1uF capacitor has good decoupling up to 6GHz. Or if you don't have the TE maybe manufacturer's graphs will convince you? http://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL05A105KA5NQN

You are already halfway to being enlightened. The first half is knowing that "best practices" are BS, the second half is knowing simulations are BS.

[OwO]

I did the simple experiment of soldering various 0603 parts directly to a SMA female connector (by sawing off all legs first) and measuring with a good VNA (not a cheapo nanovna). The results agreed with what the manufacturer's graphs say. So it's impossible that you can not get good decoupling out of a common X7R cap. How you lay out the board should also not be based on rules or simulation, but rather what you have tried and verified (with measurements) in the past. I recently designed a upright SMA to microstrip transition with almost 30dB return loss to 3GHz, and found that simulations are completely inaccurate and such results can only be achieved by experiments and a good VNA/cal kit.

[T3sl4co1l]

FYI, 3GHz is DC for @TheUnnamedNewbie.  Not sure how familiar you are with his work.

the second half is knowing simulations are BS.

Ah yes, simulations can never be correct so why even bother!  It's not like anyone has ever built anything of significance, let alone had it work perfectly the first time, using a filthy simulator!

Tim

[OwO]

So how did he conclude that discrete capacitors are ineffective beyond a few hundred MHz (which is demonstrably false)? If your simulations differ that far from reality, then I'll say it's almost useless.

[SiliconWizard]

Simulations are as good as your models are. I'm kind of questioning the models he used.

[ejeffrey]

Another thing I learned: Discrete components are pointless to do any decoupling past a few hundred MHz. Even if you ignore any layout effects, the interal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range. You just can't get around that without using special bonded capacitors meant for RF/MMIC applications. And to be frank, even if you could, your bond wires will just ruin that too. Just trust that the IC guys know their stuff and take care of decap past 100 MHz.

Or actually you know, make real life measurements that will tell you a typical 0402 1uF capacitor has good decoupling up to 6GHz. Or if you don't have the TE maybe manufacturer's graphs will convince you? http://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL05A105KA5NQN

You are already halfway to being enlightened. The first half is knowing that "best practices" are BS, the second half is knowing simulations are BS.

Trusting manufacturer graphs over simulations is terrible advice.  Even trusting your own measurements over simulation is dubious at best, but at least you know the measurement setup.  In this case, those graphs are de-embedded to the pads, and don't reflect performance in any real circuit.  They show the AC voltage across the capacitor for a given excitation current.  But nobody actually cares about the voltage across the capacitor. These models are in fact best suited for embedding into field simulators and in that capacity they are quite useful.  For directly predicting performance they are a guide to be used cautiously at best.