Electronics > Projects, Designs, and Technical Stuff
power decoupling myths
OwO:
No doubt that simulations are useful for sanity checking your work, and I use them to give a rough ballpark answer to "is this design workable" and to find pitfalls of a design that I missed (e.g. potential stability issues), but my point is you should never trust it to give an authoritative answer to "how well will this perform" or "are these vias useless". Only real world experiments can say for sure. So to tell people "get a simulator, it will teach you how to do good layouts" is bad advice, and IMO that money is better spent on good TE instead, or even just experimentation and prototypes.
TheUnnamedNewbie:
--- Quote from: OwO on July 21, 2020, 04:15:04 pm ---
--- Quote from: TheUnnamedNewbie on July 21, 2020, 03:08:48 pm ---Another thing I learned: Discrete components are pointless to do any decoupling past a few hundred MHz. Even if you ignore any layout effects, the interal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range. You just can't get around that without using special bonded capacitors meant for RF/MMIC applications. And to be frank, even if you could, your bond wires will just ruin that too. Just trust that the IC guys know their stuff and take care of decap past 100 MHz.
--- End quote ---
Or actually you know, make real life measurements that will tell you a typical 0402 1uF capacitor has good decoupling up to 6GHz. Or if you don't have the TE maybe manufacturer's graphs will convince you? http://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL05A105KA5NQN
You are already halfway to being enlightened. The first half is knowing that "best practices" are BS, the second half is knowing simulations are BS.
--- End quote ---
I stated clearly that the self-resonance was at a few hunderd MHz. Your example shows that the self-resonance is at 10 MHz (and that is usually without any pad and so on included, which will only push it further down.
If your simulations do not match your measurements, one of the two is done poorly. This can be misunderstanding how to do them, bad simulation setup, bad material properties, etc. We have desigend VCOs at 600 GHz that had a shift between measurement and simulation in the tens of MHz. So please go tell someone else he doesn't know what he is doing and that my simulations must be bad.
Now, back to my example and clarifying why there is little use in having those tiny capacitors and going nuts about your vias:
A bondwire of 1 mm is what, about 100 mOhm? Probably a good bit more at high frequencies due to skin-effect. Typical rule of thumb for bondwire inductance is 1 nH per mm. Plug that in and you find that you will have an impedance of about 600 mOhm at 100 MHz. So past 100 MHz, your chip is not gonna see a much lower supply impedance than 600 mOhm anyways. It doesn't matter if your supply impedance is 100 mOhm, 10 mOhm , or 1 nOhm at 1 GHz - your chip will just see the (at that point 6 Ohm) bondwire. Anything past a few tens to hundreds of MHz is for on-chip decoupling to solve. Sure, you can do better, and you shouldn't allow it to get horrible, but most of your decap will be done on-chip anyways.
And before you say 'But RF transistors!' - Usually, you slap a big fat inductor on your supply of the transistor to tune out the internal capacitance anyways. Probably the internal parasitic capacitance of your device is going to do more 'decoupling' than any external decap you add.
--- Quote from: SiliconWizard on July 21, 2020, 04:46:31 pm ---Simulations are as good as your models are. I'm kind of questioning the models he used.
--- End quote ---
I used high-performance models from multiple manufacturers: Samsung, TDK, Taiyo Yunden, Murata, as well as from Modelithics. They pretty much all tell you the same story, and line up with what their websites tell you. And the software and methods are the same used to design high-performance filters on PCB - there might be a few percent error, but it's not going to be an order-of-magnitude difference.
OwO:
I think we went from talking about digital ICs to RF circuits many posts ago. The #1 use case for a low impedance point on the power supply network in a RF circuit is for interference rejection, and there no bond wires come into play.
See for example this power supply filtering layout:
This is good to 6GHz, and if your models are good enough you should be able to see for yourself. The capacitors are CL05A105KA5NQN. The distance to ground plane is 0.2mm and material is FR4. You can't make a blanket statement that discrete caps are no good beyond a few hundred MHz.
OwO:
--- Quote ---the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range.
--- End quote ---
The problem with that is there is no "internal ESL" of a capacitor. Any inductance is due to the physical layout and the path that current has to follow. A wire by itself doesn't have defined inductance, and only the combination of a wire + ground plane does. I showed a few posts ago how to minimize the layout effects and in that example the impedance is mainly only due to the stub of transmission line between the DUT and the capacitor (which can be minimized by making it wide). I'm sure the manufacturer used a similar layout when characterizing the capacitor.
The SRF of a capacitor is not important. You only care about the worst case impedance across a frequency range.
TheUnnamedNewbie:
--- Quote from: OwO on July 21, 2020, 05:05:47 pm ---I think we went from talking about digital ICs to RF circuits many posts ago. The #1 use case for a low impedance point on the power supply network in a RF circuit is for interference rejection, and there no bond wires come into play.
See for example this power supply filtering layout:
(Attachment Link)
This is good to 6GHz, and if your models are good enough you should be able to see for yourself. The distance to ground plane is 0.2mm and material is FR4. You can't make a blanket statement that discrete caps are no good beyond a few hundred MHz.
--- End quote ---
I never said that discrete are no good at all. I said, and I quote:
--- Quote from: TheUnnamedNewbie on July 21, 2020, 03:08:48 pm ---
Discrete components are pointless to do any decoupling past a few hundred MHz
--- End quote ---
The topic of this is also 'power decoupling myths'. If you read my posts, you'll notice all I talked about was power supply decoupling. You are always gonna find special cases. But this entire thread of posts before was clearly about powersupply decoupling, and your posts and images implied your way was needed.
And don't try to now straw man me into being wrong by throwing the old 'but inductors need a loop' argument. You know all to well what I meant with ESL, and if you don't you aren't a very good RF engineer.
And SRF is important, because it gives you a nice point to know 'It all goes down-hill from here'.
--- Quote from: OwO on July 21, 2020, 05:13:39 pm ---
--- Quote ---the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range.
--- End quote ---
I showed a few posts ago how to minimize the layout effects and in that example the impedance is mainly only due to the stub of transmission line between the DUT and the capacitor (which can be minimized by making it wide). I'm sure the manufacturer used a similar layout when characterizing the capacitor.
--- End quote ---
Making a setup to calibrate out the inductance of your test network is trivial. We do it all the time, because that is what VNA calibration is all about. That PCB inductance is thus NOT included in the models, because if it were, the models would be all but useless for design work.
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