Electronics > Projects, Designs, and Technical Stuff
power decoupling myths
OwO:
"Discrete components are pointless to do any decoupling past a few hundred MHz" is misleading, since it's implying it's the discrete components that are no good, when the real matter is the bond wires defeating any decoupling attempts.
"the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range" is correct on its own, but within the context a reader will think you mean the internal ESL of a discrete cap makes it useless above a few hundred MHz, which I explained is incorrect. Again, SRF of 10MHz is irrelevant when the impedance is still < 5 ohms at 6GHz.
Anyway, I don't get the appeal to authority bringing up your 600GHz design, because you are designing on a process with feature size possibly 1000x smaller than on a PCB, in other words a 6GHz design on an ordinary FR4 PCB is no easier layout-wise than a 600GHz design on a 1um process. It's like telling someone to design a 1GHz circuit using a wire-wrap process that his design is "DC" to you who designs stuff with geometries 10k times smaller.
TheUnnamedNewbie:
--- Quote from: OwO on July 21, 2020, 05:28:11 pm ---"Discrete components are pointless to do any decoupling past a few hundred MHz" is misleading, since it's implying it's the discrete components that are no good, when the real matter is the bond wires defeating any decoupling attempts.
--- End quote ---
Explicitly situation the context of a statement is clearly misleading, unlike, say, showing pictures with a big red cross under a layout that is perfectly fine in 99.9% of cases, and a green check mark under a layout that has arguably way to many vias that will just make the layout a hell in any high-density situation.
iMo:
I've quickly looked at the pdfs in the first post. I did a recommendation on "3 capacitors in parallel" many times here. I saw that in an app note of ADI (as far as I can remember) long time back.
One of the issues I see with the attempt to debunk the myth is following - the ADI recommendation (and mine here as well) said explicitly you have to use 3 capacitors in 1:100 ratio, like 100p||10n||1u, etc..
Not in 1:10 as it has been elaborated above..
OwO:
The takeaway from the discussion above is that the capacitor values are not that important, it's the overall layout, and the fact that the bond wire in a typical IC defeats your decoupling attempts and you will do just as good with a single 1uF or 10uF cap in the common case of decoupling a digital IC. But if you are doing any other kind of design, the best layout should be decided on a case by case basis.
Siwastaja:
Yes, the point is, C value isn't important as long as you have enough. After you satisfy this minimum condition, you select by L.
In the past, large enough C had kind-of too much L, so you paralleled larger and smaller C to get "best of the both worlds". Said types had enough ESR to make the SFR low-impedance dips not too shallow, but combine in larger areas without so much risk of oscillation.
Now, you get large enough C with small enough L, just buy a bog-standard small-case MLCC. Say 0.47uF 0402 part, for example. So there is no reason for the paralleling trick.
Furher, the ESR of modern MLCC is so low, making Q high, that the parallel combination contains new extra risk of oscillation.
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version