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power decoupling myths

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Siwastaja:

--- Quote from: exe on July 24, 2020, 07:53:38 am ---Question: are capacitors with reverse geometry any better for decoupling? I concluded that, unless it helps to minimize track lengths, it doesn't matter. So, it should help if supply pins close to each other, but it is pointless if supply pins are far. But I've never checked this. Any opinions?

--- End quote ---

Obviously, you'll be able to squeeze the loop area a bit smaller. A small optimization.

The availability, cost, and uncertainty in second-sourcing weigh more, I'm afraid.

For general-purpose IC decoupling, this doesn't matter; you can use a 100nF 0201 for example, reversing it makes very little difference.

In power electronics with large C values this could be beneficial, though they have larger loop area caused by larger semiconductors as well so the capacitor is still a small part of that. I use quite a lot of 1206 parts when I need around 48V busses, 0805 is quite marginal, both for voltage ratings available, and amount of actual capacitance available under the DC bias. 1206 has a stupid shape, and 1210 is too big alraedy, so I'd prefer say a 0909 or 1010 instead, but the real-world availability of the parts is what drives the decision.

On the other hand, with 1206, I'm able to place additional vias for both pads under the component body, while avoiding via-in-pad. For reverse geometry, I would definitely need via-in-pad in order to exceed the performance of the 1206 design.

TheUnnamedNewbie:

--- Quote from: exe on July 24, 2020, 07:53:38 am ---Question: are capacitors with reverse geometry any better for decoupling? I concluded that, unless it helps to minimize track lengths, it doesn't matter. So, it should help if supply pins close to each other, but it is pointless if supply pins are far. But I've never checked this. Any opinions?

--- End quote ---

I think one of the bigger advantages can actually be placement, instead of loop area. The impedance is lower, because not just the loop area on PCB, but also internally in the capacitor, the plates are shorter and wider, which gives you lower ESL.

Murata had a document showing how a 'reverse geometry' cap can give you higher denstiy, because when you align them with pins, you have the narrow side of the cap near the chip. (image source: https://www.murata.com/en-global/products/capacitor/mlcc/smd/lll)

exe:

--- Quote from: TheUnnamedNewbie on July 24, 2020, 08:21:22 am ---Murata had a document showing how a 'reverse geometry' cap can give you higher denstiy, because when you align them with pins, you have the narrow side of the cap near the chip. (image source: https://www.murata.com/en-global/products/capacitor/mlcc/smd/lll)



--- End quote ---

Huh, this rises even more questions :). One is, in another thread recently people concluded that if two ICs are that close, then they can share the same decoupling cap. Sorta what murata proposes, except that there is no need to use fancy caps. What do you think?

And another question that bothers me a lot. A common best practice is to put a decoupling capacitor for each power pin. I often have one LDO supplying power to multiple ICs. Question: can these caps start resonating with each other? Or should I use a separate LDO for each potentially noisy IC? To be more specific, my typical scenario: MCU, ADC (with two power rails: analog and digital), and digital isolator on the same board.

TheUnnamedNewbie:
As I've stated a few times now, it's really impossible to make any hard guidelines. If you want to be really safe, it is likely easier to get good noise isolation by having separate LDOs for each. ADCs (or general mixed-signal chips) are a whole different can of worms with people giving contradicting advise on how to do things in terms of decoupling and supply noise. One of the issues there is that you have currents that might want to flow from the analog supply to the digital ground and vice-versa, so your loop area becomes massive for those currents. (incidentally, also why so much on-chip stuff goes differential for those applications - you have no high-frequency common-mode noise, so less common-mode noise issues)

T3sl4co1l:

--- Quote from: exe on July 24, 2020, 09:21:09 am ---Huh, this rises even more questions :). One is, in another thread recently people concluded that if two ICs are that close, then they can share the same decoupling cap. Sorta what murata proposes, except that there is no need to use fancy caps. What do you think?
--- End quote ---

"that" close = ?

If they are slow logic or analog ICs, locality of bypass won't matter.  Example: CD4000 logic, TL072 amps.  There simply isn't any energy or gain at frequencies high enough to matter; bypasses can be inches away.  (If even that: historic example, the NES controller used a, CD4021 I think, and that's literally all that's soldered to the board.  No bypass caps, just a long cable with +5V and GND, clock, strobe and data.  The controller buttons are carbon-rubber pads touching gold plated traces, and the pull-up resistors are screen-printed ink!)

74LS and HC are fast enough you'll want a cap within a few inches, but the chips being smaller than "a few inches" means a few chips can probably share.

74LVC and most <= 3.3V CMOS devices (MCUs, etc.) are fast enough that you probably want the local-at-the-pins bypass caps, and not only that but if you have heavy loads on them (e.g., MCUs and bus drivers can switch a few 100 mA at a time, through whatever combination of IO and power pins).  Wide-format capacitors may be advantageous.

The best use-case is where a plane wave needs to be shunted to ground.  The plane wave propagates along a wide transmission line or plane.  It goes into the capacitors broadside (as many lined up in parallel as needed to cover the width of the plane), then into vias to ground (arrayed opposite the plane, along the C's GND pad).

There probably aren't many practical cases where this exact situation arises...

Most loads are through narrow pins, traces or vias, and there are simply a lot of them, and not always in regular patterns.  So the best you can do is sink them all to planes, and bypass the planes at the earliest convenience.  (Example: most any device that has to be a BGA, is probably also fast enough to need immediate bypassing, but also has to be connected in this way, i.e. through an array of vias.)

A resonant stub, in RF circuitry, I think is a good example, and some have been pictured earlier in this thread I think.  The vias, capacitor and trace are all accounted for in the total length of the stub, and the trace width is held constant thanks to the wide (appropriately chosen) capacitor.  So there's no error due to lumped equivalent whatever.



--- Quote ---And another question that bothers me a lot. A common best practice is to put a decoupling capacitor for each power pin. I often have one LDO supplying power to multiple ICs. Question: can these caps start resonating with each other? Or should I use a separate LDO for each potentially noisy IC? To be more specific, my typical scenario: MCU, ADC (with two power rails: analog and digital), and digital isolator on the same board.

--- End quote ---

Can they?  Perhaps.  Draw the equivalent network and see if it does.

See, your very next question must be: what information do I need to figure it out?  Well, you don't have resonance without L and C.  What are the stray L's in the circuit?  What resistance dampens it?  What transient loads/sources might excite it?  And then you can answer these, quantitatively, by inspection of the circuit, build a model, and test it.

Tim

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