Power Supply for Higher End Processor

[Graz]

Hi All. This is my first post here. It seems like a great community, so I thought I'd ask for help.

I'm working on a design using a higher end processor. The device in question is Freescale's QorIQ P2020. I'm not phased by big buses, differential routing, length matched traces and all that, but this is by far the most complex device I've put into a design. My question is about power sequencing and supply. The reference designs I have access to all have fairly complex power management circuits. They're capable of accurate sequencing, wide input voltages, multiple voltage supplies, soft power up and down via I2C and all that. I don't think I need that. Basically, I'm going to run everything at 3.3V, except the DDR3 which needs to go at 1.5, VTT which is 0.75.

The datasheet for the device essentially says that sequencing isn't important so long as everything is up within 50ms of each other (which they will be if they're connected together). This is a wall-powered device. Power consumption and thermals are not an issue here. There is a stable, regulated +5V supply available, and as far as I can tell, I just need to step it down to 3.3V to be up and running.

With devices like this, is it possible to simplify the power supply circuit to something like an LDO regulator and a bunch of big capacitors, or do I really need the high-end supply shown in the reference designs?

[c4757p]

Huh? 3.3V? This thing at least wants a 1.05V rail for the core, PLLs, and serdes blocks. I imagine that at around a gigahertz this will have to be a hefty rail, you're not going to LDO that...

[matseng]

Ambitious project, but I suppose you won't solder the 689 ball BGA yourself?  Or did you attend the classes that DangerousPrototypes arranged in Shenzhen?

[Graz]

Huh? 3.3V? This thing at least wants a 1.05V rail for the core, PLLs, and serdes blocks. I imagine that at around a gigahertz this will have to be a hefty rail, you're not going to LDO that...

Yeah, that's right. Needs a 1.05V for core. All the IO can run at 3.3V though. I want to minimize the number of power planes. So, I guess the super-complex power system may be required. However, core power consumption peaks at ~7W at the highest available clock (at least the single-core P2010 variant does). We're not talking about a 75W+ desktop class CPU here. So I guess the question could be better phrased as, what is the most basic setup I'd need to get this thing up and running, supplying 1.05V for core, 3.3V for all IO, and the separate 1.5V for the DDR supply?

Ambitious project, but I suppose you won't solder the 689 ball BGA yourself?  Or did you attend the classes that DangerousPrototypes arranged in Shenzhen?

I may get a prototype house to do it for me. I've had some success with a rework station on smaller devices, but yeah, this is the biggest I've done by far and it'd be an expensive thing to screw up.

[AndyC_772]

Get the board assembled professionally. No question. Make sure you allow room around it for the heat sink too.

Your I/O supply shouldn't be too difficult, it's relatively low current.

The core voltage needs to be accurately controlled, and IR voltage drops will be a big deal. Personally I'm a big fan of the Enpirion range of dc-dc converters, and if you already have a good +5V rail available, they're an excellent way to generate the lower voltages locally and with good efficiency. The bigger ones have enable inputs which you can use for sequencing if you need to.

Have you done DDR memory before? If not, seek out and read Freescale's layout guidelines for DDR3, as well as any other manufacturer's application notes on the subject that you can find. Read them very thoroughly and follow them. The noise margins on DDR interfaces are much smaller than you'd hope, and they need to be maintained over a much wider bandwidth than you may have dealt with before. This has particular implications for the VTT / VREF supply, which needs to track the 1.5V rail very closely, and needs to have exceptionally low noise with a bandwidth of many hundreds of MHz.

I'll say it again because it's a really big deal: VTT is anything but 'just' a 0.75V supply rail.

Board stack-up is really important to get right too. If I recall correctly, the last PowerQuicc design I did with DDR was 12 layers, maybe 14. It's needed to escape the BGA correctly and to maintain compliant with the rule about DDR traces not crossing plane breaks.

Get it right, and these processors work very well, but there are 101 ways to get it wrong, and the result can be extremely hard to track down. Any one of a number of layout or power supply issues can cause the DDR interface to fail in ways which aren't obvious; you might have some boards which work fine, others which fail when they're hot or cold, or which crash every minute / hour / week for no apparent reason.

Good luck!!