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| Power supply topology - will it work? (Control theory, stability) |
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| Kleinstein:
There are not that many degrees of freedom in adjusting the compensation. The R5/R7 ration is relatively fixed. So there are essentially only the 3 caps c1,c2,c3 and the series resistance. The caps also are responsible for different frequency ranges: the highest frequencies are mainly influenced by C2,R6 and only a little by C1. The intermediate frequency range is influenced mainly be C1 (or more accurately by C1*R3/R1/R4*R5) and a possible resistor in series to C1. C3 is usually important for the lower frequency range - though the 100 pF value shown is rather small, but R5 is also large. So once you have a reasonable start, one can optimize the three caps relatively independent So it's not one system with 6 interacting degrees of freedom - which would really be hard, but more like 3 systems with 1 or 2 parameters with relatively little interaction. Optimization is still not easy and will take some time and simulation runs. One may not find the absolute best - but defining what is best is already difficult. It will be a compromise on performance at different loads and tolerance to parasitic effects and not so perfect models. It does not make sense to optimize to far in the simulation, as really life will be a little different - so it also has to work with slightly values. The more annoying part is that the "best" parameters also depend on the DC current. So one has to find a solution that works at high and low currents. Here it can really help to have the output stage in a way that it depends less on the current: this could be an extra local loop or maybe using feedback from the source resistor instead of the gate driving part. If performance of low currents is important, I would consider using a output stage that can work 2 quadrants. The next possibly tricky part could be nonlinear effects do to a kind of windup of the regulation loop - so sometimes even if everything is fine for small signal tests, the a regulator circuit can still oscillate after large steps with certain loads. However this also applies to other topology. It can be still a little tricky when doing it with hardware, unless you have good instrumentation (response analyzer). However in the simulation no limitations from instrumentation: for example one can still get the loop gain for an unstable system. So one can directly read loop gain or output impedance or step response. Having a regulator of emitter follower / source follower type can be a little easier to tune - at least if you don't need a lab supply that includes current regulation too. |
| Jay_Diddy_B:
Hi, Let me see if I can explain how to do analyze this. Modified Model I have rearranged the model, without changing the circuit or the component values. I have added labels OP_U1 and OP_U2. I have divided the circuit into three blocks, the power stage, error amplifier and the divider stage. The loop gain is the product of the gain of all three stages. Results The results show that the error amplifier has a single pole slope, 20 dB/decade and 90 degrees of phase shift. The result deviates from this at high frequency because of limitations in the op-amp. The divider stage has a pole zero pair. This is often used in power supplies to generate phase advance or phase boost. Again the result is textbook, until the op-amp characteristics creep in at the higher frequencies. The output stage is the most interesting. The other blocks, nothing changes with load current, output capacitance etc. but in the power stage everything matters. The Power stage is a single pole from the output capacitance and the transconductance of the MOSFET. There is also a zero formed by Cout and the ESR of the output capacitor. Changing Cout I have introduced the .step directive to change the value of the output capacitor through a list of values. Results from Changing Cout. I hope this give a little insight in to how to model this circuit. Regards, Jay_Diddy_B |
| Yansi:
Thank you for detailed explanation how to simulate the loop stability. Will install the spice soon and try to bite it. Currently the soledering iron is still the easiest for me. :-/O I have finished building the load step test jig, so I can finally measure the response. The setup was as follows: Schematic with values attached. Input is around 260V, output set to 70V. Load switched on-off is 1k65 resistor (so 42mA or nothing). Step responses shown below. Tested first with 1uF 1ohm only, then added 10uF ellytic cap directly on the output (no "additional ESR"). Could you please evaluate the results, somehow? I am not sure how that should look like when correct, but I am concerned the ringing when load is switched OFF is really not good. I have tried fiddling with C3 and C1, increasing their values slightly (up to 0,5nF or so), but not much effect on the step responses. Increasing C3 too much (0,6n) makes it oscillate. Note the very long ringing time (and period) at load off, especially with the additional 10uF cap. I will also try stepping the load between 20 and 40mA, what will be the difference. Thanks, Yan EDIT: Schematic added. Note V2=875mV. |
| Jay_Diddy_B:
Yansi and the group, I ran the transient test with this model, 10uF capacitor: Here are the results: Fairly similar to what you have on the hardware. Modified Model I have modified the model to improve the response: Here are results from the modified model: Try modifying the hardware and see if you get a similar result. You may need to add load resistor, around 1mA to set a minimum output current. Regards, Jay_Diddy_B |
| Kleinstein:
Doing the step response all the way to zero current is difficult for the regulator. Some of the ringing when switching the load off can be from nonlinear effects (having the MOSFET turned off for some time). This might need additional measures. Also the MOSFET gets quite slow with only the 800 K from the divider as a load. The LM324 is a quite slow OP and thus one can not expect a very fast response. To avoid the dead band from the output stages one could try an additional 1-2 K to GND at the OPs, especially OP1. A faster OP (like TLC272) could help. The response is relatively slow, but much of this can be attributed to the slow OPs. One could ease a little on the OPs by reducing R1 to maybe 5 Ohms. Some ringing like with the 10 µF capacitive load is normal and cannot be avoided. However the slow ringing indicates a still slow regulator and normally such heavy ringing should only happen with much larger caps (like 1000 µF). |
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