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Power supply topology - will it work? (Control theory, stability)
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Yansi:
Hi!

I am using X2 rated caps in the circuit, as I have many of those available and they are sufficient with voltage rating.
Currently the output cap is an 1uF MKT from Vishay, so not polypropylene but polyester: http://www.vishay.com/docs/28161/f1772x2.pdf
It has a an added series resistor of 1ohm, as you did recommend in the beginning.






Jay_Diddy_B:

--- Quote from: salbayeng on November 20, 2016, 06:38:10 am ---Yea, you're right, of course.  (an improvement on "right off course" :-DD)
I first looked at the output stage and thought to myself , "the output impedance is just R1 (as the MOSFET that shunts it in current mode is effectively infinite impedance)"
It's obvious if you consider the output swings 100's of volts but only a few volts across R1.
The maximum gain (at DC obviously) is simply 100k/R1.

The simple circuit you have is sufficient to explain what is going on.
I would add the embellishment of
(a) the gate resistor and miller capacitance but guessing 300R and 1nF  puts a pole in at 500kHz, of no concern
(b) and also add the zero due to ESR 100uF + 1R is only 1.6kHz (I should probably find some real capacitor data and not guess!)

--- End quote ---

Just to clarify this further.

You may not have seen this circuit before:



But if you rearrange the parts:



It begins to look familiar.



You have probably seen this before:



It is a textbook common emitter amplifier.

If you ignore Cout, the simplified voltage gain of this stage is Rcollector / Remitter.


The challenge with designing a (bench) power supply, is that you don't know what value of Cout or Rload somebody will attach. The load may not be a resistor. If the load is a constant current load the gain can be very high.

If you designing a power supply where the load and capacitance is know, it is a little easier.

Regards,

Jay_Diddy_B

Yansi:
Hi! A little update: As the current limiter is working just fine, I left it alone and have begun working on the preregulator control loop.

Before I started with the preregulator, I have noticed an unseen problem in the circuit (you can skip if you want, really nothing serious or much interesting, easy solution):
Way back when we discussed how to merge the two regulator outputs, we had the choice between resistor or CC load for the emitter follower. The resistor works fine, sure, but there is a problem! If the regulator output goes into positive saturation (like "not enough input voltage"), the resistor in the emitter of the follower will get blown after a while:  It was calculated for 30mA at round about 6V gate voltage, which is fine. However when the saturation occurs full voltage (like almost 11V) appears on it and high current is gonna destroy it. So the CC load might be a better solution, than an over engineered (1 or even 2W) resistor, that won't see more than 0.2W very often. The overload is somewhere about 0.8W so 1W resistor is not such a big deal. But just wanted to point that out.

Preregulator: Is a textbook standard inverted buck (switch and choke in the negative rail, positive common) controlled by an UC3843. I have successfully tuned the opamp that controls the preregulator. Partial schematic attached. Vds is a voltage sensed from a mosfet drain, ground is still the positive output terminal. Works quite good.
Step response of the preregulator output is also attached. Supply set to 75V, then shorted for a moment. Preregulator holds constant 50V over the mosfet. The undershoot is about 6V, no big deal - caused very probably by a windup of the integrator - as the ramp down speed is limited by the discharge rate of the prereg output cap (depends on supply output current).
The LED on the schematic is an optocoupler to the COMP pin of UC3843. There is a mistake in the drawing, the LED should be connected of course against +12V, not ground (otherwise the polarity of the feedback is wrong).

Slight problem 1: At some level of PWM, the current mode control of the buck convertor is still very slightly unstable (at the currentmode side of thing - subharmonic oscillation, even though I tried to apply a slope compensation. (Maybe doing it wrong or completely another problem).  I will draw the complete schematic so we can look more in detail, where the problem might be.

Another slight problem 2: After adding the drain voltage sense divider, you know, across the mosfet... guess what, current flows to the PSU output even when the mosfet is fully closed. Meaning, when the PSU is unloaded, quite some volts are present - 180V or so to be exact. (voltage divider is formed from the two voltage sense dividers 800k / (800k+330k+22k) * LinregInputVoltage).
Now what to do with it? Low value resistor accross PSU output terminals is not a solution, due to very wide voltage range (the parasitic current flowing from up top is constant (as the Vds voltage is also constant), about 0.15mA. A small CC load on the PSU output would do. What do you think?

Thanks,
Yan
salbayeng:
re problem 2:
If your switching regulator is connected to the real negative ground,  then use two matched voltage dividers, one for the prereg voltage, other for the drain voltage, and use the difference of these. With a bit of cunning you can bleed your setpoint voltage into one of these legs. So it's just one opamp needed.
The problem of the output floating up is to be expected, (and you will get leakage current in mosfet and on PCB's particularly with heat, moisture, aging, lint buildup) I looked at this and didn't have an elegant solution (else I would have posted it) , you need a Ptype device, but there is no footroom to drive it. possibly lifting the bottom leg of R1 by a few volts would allow a PMOS to be activated

Also note for the dropper resistor in the divider, use 3 or 4 in series , allow for no more than 200v per resistor, and ensure you use metal oxide resistors, rated at 300v.

re the first problem:
Cheapest is sometimes the best; use a 2w resistor is a viable option, there are some axial types in 1W package sizes, they get stinking hot, they have really thin steel wires so the body can be 250C, but not conduct enough heat to melt the solder.
You could use back to back diodes across the integrator cap, but difficult to decide which voltage to use, and you would need the low If, low leakage variety. Note this saturation problem is vaguely related to your problem 2 , like many elegant designs, things get real ugly when you have to contend with all the exception handling.

Kleinstein:
To compensate the leakage current or current through the drain-source sensing circuit, one could add a constant current load to the output. One can use the (supposedly 12 V) supply for the OPs for this to provide headroom to make it work down to zero:

Have a PNP transistor with base connected to GND, a resistor (e.g. 10 K) from the +12 V (preferably regulated) to the emitter and the collector to the negative output. This would provide something like a 1.1 mA constant load, working down to about - 600 mV. So to avoid the possibility to get a slightly negative output one could lift the base to that about 600 mV (e.g. one diode drop - saturation voltage of the PNP). As the current from sensing the DS voltage is pretty constant one can compensate this also.
Unless for very high voltages the pre-regualtor should be set for much lower DS voltage. Usually something like 3-10 V should be enough. It is just to have some reserve in case the preregualtor can not follow fast enough. There should also be an filter between the two stage, to keep RF noise out.

For the gate drive, it might be a good idea to have a fixed maximum voltage limit for the gate - this would also act as an independent fast acting instant current limit, though not accurate.
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