Electronics > Projects, Designs, and Technical Stuff
Power supply topology - will it work? (Control theory, stability)
salbayeng:
I've combined , (and hopefully improved upon) Kleinstein's ideas.
(a) Inherent current limit of the main MOSFET (Q1) in my schematic , by voltage limiting the gate (to 12v in my schematic) , and setting the emitter resistors R4+R5 to produce the appropriate current limit. I've added C1 so there is a fast current limit of ~ 20mA to charge up the output cap , and a slow limit of 5mA, obviously you can adjust these values as required.
(b) constant current pull down this is Q3 in my schematic (could be a PNP , I didn't have any HV PNP in my model library, and too lazy to import a model) , for a fixed current , connect gate to gnd, and omit D1, set R2 to 10k, and that's the 1.1mA source Kleinstein refers to.
I've embellished it so it only comes on when the capacitor needs discharging. The big problem with my approach is the crossover, and discharge current is achieved by subtracting 2 x Vth and a zener drop from 12v, so if any of these move around much it won't be accurate.
You could also split R2, and add a speed up cap just like C1 if you were that way inclined.
I've also set resistor values so the error voltage can swing through the entire 12v available , and now the upper 4-12v region controls the charging current, and the range below 4v controls discharge , given the mosfets have ~ 4v this went together better than I expected, so we have basically a class AB amplifier stage.
The simulation produced excellent response with no feedback around X1, although Verror was oscillating ~ 1MHz!
I took a wild stab at some compensation values, and it's pretty good now as shown with 100k & 1n , the opamp gain is 100 above 1.6kHz . and an integrator below that
The step response overshoot is about 1v at 300v ,slightly underdamped ,ringing at ~1kHz ( I repeated sim with smaller timestep and relative accuracy and its still similar looking, so the sim might be believable!)
The closed loop responses attached (blue = 3meg, red=30k load) shouldn't be trusted, I'm not sure where the bias point is . The blue one corresponds to the observed step response.
The sim just applies a step change in the setpoint to and from 70v to 320v, I've stepped the load from 30k to 3meg, with 30k you can see the current limiting taking place, and you can only sustain ~ 140v across the 30k while in current limit mode.
There are figures attached for the output voltage, current, error voltage, and drain voltages.
salbayeng:
Ok , I've managed loop gain plot (Using Jay_Diddy method), see pdf.
I've done this with 3 load resistors, 30k, 300k,3meg red green blue for loop gain , and light shades of same for phase.
The 30k & 300k are pretty much under each other , the 3meg is different , presumably the mosfets are biased into a cross-over dead spot?
The phase at 0.01Hz starts at 180deg , and the gains level off (as the op-amp maxes out its gain)
According to the plot, loop gain is 0dB ~ 2.5kHz, with phase ~ 55deg.
Kleinstein:
Adding a P-MOSFET in the way salbayeng did, is adding limited 2 quadrant operation. This can be an big advantage when is comes to recovery from large disturbance. This version needs an stable 12 V (preferably a little lower) supply and might be a little sensitive to thermal drift. The zener diode would need an individual adjustment, depending on the FETs to keep the dead zone small or even ensure class AB operation.
Adding the phase boost with splitting the source resistor is less practical. One thing is that it need a quite sizable capacitor, if R5 is in a much smaller more realistic range (e.g. 1-10 Ohms). The advantage of having the phase boost in the feedback divider is that it also reduced the bandwidth requirement for the OP and together with protection diodes it helps with the CC to CV transition without much overshoot (tends to be a little slow instead).
salbayeng:
Yep I acknowledge it's not perfect, I just scribbled it on bit of paper to see if I could avoid having a current source on all the time, by simply moving Q3 gate drive across,
I tried it on a sim and it worked better than I expected so I printed some epictures off and pushed it here for comment.
The "emitter bypass" cap wasn't primarily for phase boost, I would expect to use a shunt cap on the feedback for phase boost to improve HF regulation.
I had it working open loop just driving a trapezoid pulse into the gates, and it worked well, so just closed the loop as simply as possibly, R11 and C3 are the default values Simetrix drops in, and 100k gives a gain of 100 which seemed appropriate, I wasn't trying to get an optimal controller, just wanted to see how well the crossover worked with a closed loop, heck even the 4.7v zener is the default zener, and I fluked about 100mV crossover overlap. Q3 is only a 50v MOSFET, but a quick edit of the spice file fixed that!.
The 1k / 500uF is intended to provide a time constant of 500ms, to approximate the thermal time constant of Q1, so it can draw more current for short periods of time.
While pea-size 560uf/6.3v caps are available as polymer dielectrics, this brute force approach is unweildy with say 100R as the source resistor.
And you could do the "anti-surge" feature using smaller capacitors, a handful of resistors and a zener in the gate drive but it's less elegant.
I've used the PMOS threshold before (as a 3.8v reference voltage) to set pullup current in some active terminators in another project, and over ~ 60 units there was a 5% spread in actual currents, better than I expected , and those current sources also used an elegant method to reduce power consumption when not actively switching.
Kleinstein:
The source resistor should be much smaller - even the 22 Ohms that the OP used are relatively large. Otherwise too much voltage (and power) is lost there. For the P-MOS the source resistor might be relatively large and the capacitor to boost the current for short times might be viable.
For a short time current limit a zener right at the output of the OP (or where the CC and CV signals are combined with diodes) is more effective. There just is no need for a very high gate voltage. This would also save the small resistor at the emitter follower.
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