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Offline cyberfishTopic starter

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Powering FPGA
« on: November 12, 2010, 06:56:09 pm »
I'm designing an FPGA board, using a TQFP-208 Spartan-3E, and am thinking about how to power it.

There are 3 voltages -
1.2V for Vccint (internal)
2.5V for Vccaux (auxiliary)
2.5V for Vcco_1 (powers output buffers for the bank connected to DDR memory)
3.3V for Vcco_other (powers output buffers for other banks)

Each of them have 4-6 pins, on all sides of the FPGA.

I'm trying to do this on a 2 layer (though might be a good idea to at least go 4 layer) board, so obviously routing power becomes problematic.

Xilinx application notes say all the power pins are connected internally, but the best practice is to still connect them all externally, and bypass them individually, so internal impedances won't degrade the supply voltages at high current.

However, all those application notes are for Virtex, running at presumably much higher frequency. My design will only be run at 133Mhz max (fastest clock domain).

Do you think it'd be fine to just have power enter on 2-3 pins of every rail, but put caps on all pins?

Since I don't have a power plane, would it really make sense to connect all the voltage pins (of the same level) together externally, probably under the FPGA? I'm guessing the impedance won't be much lower than internal connections.

What do you think?

Thanks
 

Offline TechGuy

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Re: Powering FPGA
« Reply #1 on: November 12, 2010, 07:38:33 pm »
I'm designing an FPGA board, using a TQFP-208 Spartan-3E, and am thinking about how to power it.

There are 3 voltages -
1.2V for Vccint (internal)
2.5V for Vccaux (auxiliary)
2.5V for Vcco_1 (powers output buffers for the bank connected to DDR memory)
3.3V for Vcco_other (powers output buffers for other banks)

Each of them have 4-6 pins, on all sides of the FPGA.

I'm trying to do this on a 2 layer (though might be a good idea to at least go 4 layer) board, so obviously routing power becomes problematic.

Xilinx application notes say all the power pins are connected internally, but the best practice is to still connect them all externally, and bypass them individually, so internal impedances won't degrade the supply voltages at high current.

However, all those application notes are for Virtex, running at presumably much higher frequency. My design will only be run at 133Mhz max (fastest clock domain).

Do you think it'd be fine to just have power enter on 2-3 pins of every rail, but put caps on all pins?

Since I don't have a power plane, would it really make sense to connect all the voltage pins (of the same level) together externally, probably under the FPGA? I'm guessing the impedance won't be much lower than internal connections.

What do you think?

Thanks


I would connect all of them to power. Nothing sucks more that having to re make your PCB because of an error!

For TQFP devices I connect all of the power pins internal (under the chip and I place most of the decoupling caps on the solder side underneath the chip so all of the connections are super short. I usually run in a single trace for power which to connect the them all using the internal (underneath the chip) traces. (I've attached an example -showing the solder side with 0804 decoupling caps)

If you can't route all of the traces because of all the different voltages with a two layer board and this is just a one-off development board, I have used wirewrap wire soldered into via's provide additional virtual layers to get by. This works out fine if all you need is a few extra traces. Use vias and not try to solder wirewrap directly on the chip because its a real pain! Its very easy to stick the 30 gauge wirewrap into a small via. and solder it.
 

Offline Balaur

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Re: Powering FPGA
« Reply #2 on: November 12, 2010, 07:39:07 pm »
Hello,

IMHO, power management will make or break a design.

According to the specifics of your circuit, you could reasonably supply only a few pins/bank.
However, I do think that there is no need to do that, since powering & decoupling all the pins is fairly feasible.

As an example, I've worked once on an economical 2-layers board with a MQFP-176 IC and several TSOPs. The PCB guy routed very nicely the core/pads and several other less important supply rails under the MQFP and then "via-ed" them to death to the other side where decoupling capacitors were connected. This leaves the top periphery of the chip free to route the active signals. We didn't found any particular problems with this implementation.

Cheers
 

Offline jahonen

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Re: Powering FPGA
« Reply #3 on: November 12, 2010, 07:55:58 pm »
However, all those application notes are for Virtex, running at presumably much higher frequency. My design will only be run at 133Mhz max (fastest clock domain).

Do you think it'd be fine to just have power enter on 2-3 pins of every rail, but put caps on all pins?

Since I don't have a power plane, would it really make sense to connect all the voltage pins (of the same level) together externally, probably under the FPGA? I'm guessing the impedance won't be much lower than internal connections.

What do you think?

Thanks

It is not the frequency that kills, it is the signal edge rate. Leaving especially IO-power pins unconnected is not probably wise. It might cause strange pattern and data-dependent SSN problems. Especially with DDR memories, which has relatively small noise margins on the signal levels. DDR interface would like also to have proper impedance controlled transmission lines, which is difficult to achieve with two-side board, unless you make your board very thin (>=0.2 mm), and can dedicate other side to contiguous ground plane. Crosstalk might also be too large. Also, one should only use ground for reference plane for DDR traces.

Regards,
Janne
 

Offline cybergibbons

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Re: Powering FPGA
« Reply #4 on: November 12, 2010, 08:39:45 pm »
I'm from an Altera background, but have seen people cut corners on power and regret it.

If you already have a design, it may be possible to cut back. But it's really hard to predict - certain blocks and designs can draw a lot more power than expected. I also found having two totally independent systems on the same chip could cause horrible cycling power draws when the transitions ended up coming in and out of lockstep.

Even the dev boards from Altera can't supply the full current that the chip can draw - I had to bulk up both the power supply and cooling on a project.
 

Offline hans

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Re: Powering FPGA
« Reply #5 on: November 12, 2010, 08:56:04 pm »
I wouldn't recommended it. All of the power would have to go through only a couple of pins, and a couple of PCB wires, which are likely to very small in high pin density devices. If your for example look at power MOSFETs in SMD format, they might come in unusual packages like QFN8, but have the same functionality pin multiple times.

Please note that 133MHz is a high speed design. Decoupling is essential for such devices. I suggest you should either go 4 layer if you want the design to stay compact or consider sizing up your board so you can properly do the decoupling. Always remember that decoupling should be something you should draw out first before you're going to lay out signals. It's not that your decoupling caps would be placed further back because some signal lines have to make a tight bend.
 

Offline cyberfishTopic starter

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Re: Powering FPGA
« Reply #6 on: November 12, 2010, 10:36:52 pm »
Thanks for the great advices!

I guess it's general consensus that it's a bad idea to cut this corner. I will keep it then.

Decoupling caps (I'm thinking 0805, since I'm hand soldering) could be problematic in space. I want the DDR RAM chip to be very close to the FPGA since there will be 133MHz signals running down those traces. I guess for those caps in the way I will just move them to solder layer as suggested. I don't usually want to do that because I thought vias increase the inductance.

The DDR interface is the only high speed signal on the board level. Everything else will be <10MHz (well, maybe except the configuration signals).

And upon some more investigation, it appears like all my other components can do 2.5V I/O also, so I'll be able to get rid of the 3.3V rail. That leaves me with just 2 voltages - 1.2V and 2.5V. Should be a lot easier.

I know nothing about chip design, but I thought there would be something like a power plane and ground plane on the chip level. Is that not true?
 

Offline mikeselectricstuff

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Re: Powering FPGA
« Reply #7 on: November 12, 2010, 11:07:53 pm »
At that sort of frequency and number of supply rails, 4-layer is going to be pretty much essential, if only to maintain a solid ground layer.
4L may also allow fewer decouplers to be used as inductance between power & ground pins will be greatly reduced.

2 layers is sometimes possible where you have only 2 supplies, favourable signal routing and low-ish frequency. You still need a reasonably solid groundplane, so you are mostly routing one one layer.
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Offline allanw

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Re: Powering FPGA
« Reply #8 on: November 13, 2010, 12:09:56 am »
Try going smaller then. I've found that 0603's aren't much more difficult than 0805's. And 0402 is possible even with a huge iron tip and no magnification. You only need a really good tweezer to hold the chip still.
 

Offline mikeselectricstuff

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Re: Powering FPGA
« Reply #9 on: November 13, 2010, 10:22:18 am »
Thanks for the great advices!

I guess it's general consensus that it's a bad idea to cut this corner. I will keep it then.

Decoupling caps (I'm thinking 0805, since I'm hand soldering) could be problematic in space. I want the DDR RAM chip to be very close to the FPGA since there will be 133MHz signals running down those traces. I guess for those caps in the way I will just move them to solder layer as suggested. I don't usually want to do that because I thought vias increase the inductance.

The DDR interface is the only high speed signal on the board level. Everything else will be <10MHz (well, maybe except the configuration signals).

And upon some more investigation, it appears like all my other components can do 2.5V I/O also, so I'll be able to get rid of the 3.3V rail. That leaves me with just 2 voltages - 1.2V and 2.5V. Should be a lot easier.

I know nothing about chip design, but I thought there would be something like a power plane and ground plane on the chip level. Is that not true?
Don't know but it won't have an impedance as low as the  1oz copper on your PCB.
Re.decouplers remember larger sizes will have higher inductance - 0603s are a good balance between hand-assembleability and size. Also remember vias add inductance, so the optimum routing is with teh cams on teh same side as the chip, chip pin-cap-via to powerplane

With 2 supplies and fast stuff only in a small area you may just be able to manage 2 layers depending on the locations of the 1.2v pins. You may need to go down to 0402 caps though.

However the extra cost of 4L will probably be repaid by time saved in layout. And if it's something headed for production where you care more about cost, start with 4L for testing/debug so you minimise the chance of chasing noise issues, then once everything is working look at doing a neew 2L layout. 
Remember that a  4L may end up smaller, which will partly offset the extra layer cost.
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Offline Neilm

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Re: Powering FPGA
« Reply #10 on: November 14, 2010, 08:28:25 pm »

The DDR interface is the only high speed signal on the board level. Everything else will be <10MHz (well, maybe except the configuration signals).


It is not the frequency of the signal that matters - it is the speed of the edge transition. I was in the position a few years ago using a CPLD. We had a low frequency signal (3Hz) that caused problems when it happened as the edge transiition was so fast (and the routing so poor) it caused a voltage spike on the rail. The result was the signal was corrupt and I got random transitions instead of a nice wave.

If you are aim to sell the product in Europe it will have to pass EMC regulations, what ones will depend on the product you are making. when these changed for my industry a few years ago I was charged with going trhough those products that were non-compliant with the new standard.

I have seen many examples of people trying to save money by comprimising on the BOM cost. Even if you did manage to get the thing working with 2 layers you might find that the money you saved by going that route will be lost by having to retest, redesign or actually pushing up the price as you add ferrites into the unit to get it to pass.

I have done some design with Xilinx chips - the applications notes are quite comprehensive (and a bit confusing at first) but they are very useful and if you follow them you should not have a problem.

If you need additional resouce on board layout I recommend http://www.compliance-club.com/. Look for articals from Keith Armstrong. I have followed these on several occasions and have not had many problems, especially with high speed signals. When I read them it highlighted several things that I was not aware of, or had not realised that they could make as much differance as they do.

Yours

Neil

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Offline cyberfishTopic starter

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Re: Powering FPGA
« Reply #11 on: November 14, 2010, 11:59:46 pm »
Thanks for the good information.

This is a hobbyist project, so I'm not really worried about EMI and such.

The problem with 4 layer is, at prototyping quantities, it's very expensive, or have insane lead time, or both. Most fab houses won't even do 4 layers for low quantities.
 

Offline Zad

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Re: Powering FPGA
« Reply #12 on: November 15, 2010, 02:14:12 am »
For a hobby project, if you ran out of power line space on the ground plane, you could probably bring the power pins through on vias and decoupling caps, and wire up the power with good old tinned copper equipment wire. I think sometimes we get so distracted with doing things neatly and "correctly" by routing lines all over the place, that we forget that a wire link is often a perfectly valid solution.


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