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Powering FPGA

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cyberfish:
I'm designing an FPGA board, using a TQFP-208 Spartan-3E, and am thinking about how to power it.

There are 3 voltages -
1.2V for Vccint (internal)
2.5V for Vccaux (auxiliary)
2.5V for Vcco_1 (powers output buffers for the bank connected to DDR memory)
3.3V for Vcco_other (powers output buffers for other banks)

Each of them have 4-6 pins, on all sides of the FPGA.

I'm trying to do this on a 2 layer (though might be a good idea to at least go 4 layer) board, so obviously routing power becomes problematic.

Xilinx application notes say all the power pins are connected internally, but the best practice is to still connect them all externally, and bypass them individually, so internal impedances won't degrade the supply voltages at high current.

However, all those application notes are for Virtex, running at presumably much higher frequency. My design will only be run at 133Mhz max (fastest clock domain).

Do you think it'd be fine to just have power enter on 2-3 pins of every rail, but put caps on all pins?

Since I don't have a power plane, would it really make sense to connect all the voltage pins (of the same level) together externally, probably under the FPGA? I'm guessing the impedance won't be much lower than internal connections.

What do you think?

Thanks

TechGuy:

--- Quote from: cyberfish on November 12, 2010, 06:56:09 pm ---I'm designing an FPGA board, using a TQFP-208 Spartan-3E, and am thinking about how to power it.

There are 3 voltages -
1.2V for Vccint (internal)
2.5V for Vccaux (auxiliary)
2.5V for Vcco_1 (powers output buffers for the bank connected to DDR memory)
3.3V for Vcco_other (powers output buffers for other banks)

Each of them have 4-6 pins, on all sides of the FPGA.

I'm trying to do this on a 2 layer (though might be a good idea to at least go 4 layer) board, so obviously routing power becomes problematic.

Xilinx application notes say all the power pins are connected internally, but the best practice is to still connect them all externally, and bypass them individually, so internal impedances won't degrade the supply voltages at high current.

However, all those application notes are for Virtex, running at presumably much higher frequency. My design will only be run at 133Mhz max (fastest clock domain).

Do you think it'd be fine to just have power enter on 2-3 pins of every rail, but put caps on all pins?

Since I don't have a power plane, would it really make sense to connect all the voltage pins (of the same level) together externally, probably under the FPGA? I'm guessing the impedance won't be much lower than internal connections.

What do you think?

Thanks

--- End quote ---


I would connect all of them to power. Nothing sucks more that having to re make your PCB because of an error!

For TQFP devices I connect all of the power pins internal (under the chip and I place most of the decoupling caps on the solder side underneath the chip so all of the connections are super short. I usually run in a single trace for power which to connect the them all using the internal (underneath the chip) traces. (I've attached an example -showing the solder side with 0804 decoupling caps)

If you can't route all of the traces because of all the different voltages with a two layer board and this is just a one-off development board, I have used wirewrap wire soldered into via's provide additional virtual layers to get by. This works out fine if all you need is a few extra traces. Use vias and not try to solder wirewrap directly on the chip because its a real pain! Its very easy to stick the 30 gauge wirewrap into a small via. and solder it.

Balaur:
Hello,

IMHO, power management will make or break a design.

According to the specifics of your circuit, you could reasonably supply only a few pins/bank.
However, I do think that there is no need to do that, since powering & decoupling all the pins is fairly feasible.

As an example, I've worked once on an economical 2-layers board with a MQFP-176 IC and several TSOPs. The PCB guy routed very nicely the core/pads and several other less important supply rails under the MQFP and then "via-ed" them to death to the other side where decoupling capacitors were connected. This leaves the top periphery of the chip free to route the active signals. We didn't found any particular problems with this implementation.

Cheers

jahonen:

--- Quote from: cyberfish on November 12, 2010, 06:56:09 pm ---However, all those application notes are for Virtex, running at presumably much higher frequency. My design will only be run at 133Mhz max (fastest clock domain).

Do you think it'd be fine to just have power enter on 2-3 pins of every rail, but put caps on all pins?

Since I don't have a power plane, would it really make sense to connect all the voltage pins (of the same level) together externally, probably under the FPGA? I'm guessing the impedance won't be much lower than internal connections.

What do you think?

Thanks

--- End quote ---

It is not the frequency that kills, it is the signal edge rate. Leaving especially IO-power pins unconnected is not probably wise. It might cause strange pattern and data-dependent SSN problems. Especially with DDR memories, which has relatively small noise margins on the signal levels. DDR interface would like also to have proper impedance controlled transmission lines, which is difficult to achieve with two-side board, unless you make your board very thin (>=0.2 mm), and can dedicate other side to contiguous ground plane. Crosstalk might also be too large. Also, one should only use ground for reference plane for DDR traces.

Regards,
Janne

cybergibbons:
I'm from an Altera background, but have seen people cut corners on power and regret it.

If you already have a design, it may be possible to cut back. But it's really hard to predict - certain blocks and designs can draw a lot more power than expected. I also found having two totally independent systems on the same chip could cause horrible cycling power draws when the transitions ended up coming in and out of lockstep.

Even the dev boards from Altera can't supply the full current that the chip can draw - I had to bulk up both the power supply and cooling on a project.

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