Precision Current Sink - I found a Gem of a Circuit

[mawyatt]

I saw this in a design idea from Christian de Godzinsky in EDN in 2006.
https://www.edn.com/error-compensation-improves-bipolar-current-sinks/
It extends the idea with and improved compensation scheme. Works a treat as I recall.
Can it deal with nasty Idss leakage in mosfets I wonder if temperature compensation would be usefull here.
I'm sure one of you guys will have a go at that.

The EDN article is referenced in post #3 above.

The Idss leakage should be handled by the normal circuit configuration since the leakage from MOSFET Drain to Source flows thru the sense resistor and controlled by the "normal loop" behavior. Same should be true for a Bipolar Transistor with Collect to Emitter leakage.

Agree, we're sure "Somebody" will play around with this, it's too intriguing a circuit

Best

[UnijunctionTransistor]

This circuit has intrigued me enough to simulate it. Works great!

Of particular interest, is how to parallel at least two power pass transistors. On a real world implementation, for SOA considerations, one would very likely require two or more pass transistors. I am still in the “play with the circuit” phase.

[mawyatt]

This circuit has intrigued me enough to simulate it. Works great!

Of particular interest, is how to parallel at least two power pass transistors. On a real world implementation, for SOA considerations, one would very likely require two or more pass transistors. I am still in the “play with the circuit” phase.

This circuit has intrigued me enough to build it. Works great! 

Terry knew we couldn't resist

Even on a Protoboard with just 1% resistors, OP-07 and a TIP-41, using a 10-Turn Pot with Dial as the input

Just add a small emitter resistor to the parallel power bipolar devices for higher currents. You shouldn't need to "split up" the output devices with separate control if the emitter degeneration is designed properly. One could probably use a "Quasi" Darlington where one input transistor feeds a pair of power transistors with emitter degeneration. Just make sure that all the base "effective" currents flow thru the Op-Amp output series resistor, this is the only way to get proper base current compensation.

Best

[Benta]

A comeback from the OP.
I'm gratified and a little bit surprised that this little circuit has inspired people this much.

I played around with the simulations as well and found the same result as mawyatt: the sense resistor sets the precision (obviously), but the other resistor ratios are rather uncritical, as are their precision.
The classical way of analyzing that (which I'm sure Carl Nelson did) is to find partial derivatives for the component sensitivities. I'm too lazy to do that myself today (was curriculum in the late 80s)
Simulators rock for that.

Thumbs up for analog electronics and circuit gems. I hope to find more. 

[mawyatt]

If one followed thru with the partial derivatives for component sensitivities, all the resistors except the sense resistor should have an output current sensitivity of at least 1/(Effective Beta) wrt the sense resistor. Effective Beta is Io/Ii of the output device type.

The sense resistor obviously has a sensitivity of 1 to the output current, and also has the most temperature sensitivity, so this becomes the limiting component in this precision source.

Anyway, thanks for posting this very intriguing circuit!!

Best

[UnijunctionTransistor]

This circuit has intrigued me enough to build it. Works great! 

Terry knew we couldn't resist

Just add a small emitter resistor to the parallel power bipolar devices for higher currents.

You mean like so?

[mawyatt]

Yes.

If you need a Darlington for lower base current then you can use 1 transistor in front of the pair.

Edit: Another option with higher current output transistors instead of a Darlington is to move the Darlington input transistor "inside" the control loop with the op-amp output with the collector connected to Vcc. This acts as a buffer for the op-amp output to reduce op-amp output current demands. With this configuration the output load current can be from a supply less than 0.3V and still maintains constant current throughout the output supply range.

Best

[RoGeorge]

Trying to avoid the 6 ratio matched resistors (with one of them being a power resistor), here's my take on it:



Made a copy of the base current, then drained the same amount from the collector, thus making Ic=Ie.
Problem solved, and easier to integrate (matched transistors are almost trivial in an IC).
Might work much faster (but I didn't check), because all is current controlled, no M\$\Omega\$ resistors.

 

[mawyatt]

Interesting idea, some simulations should show how well behaved this is.

Edit: You'll need a diode across the PNP Reference transistor to allow the op-amp to turn off the output device. Consider building and testing this, would be interesting to see how well it behaves and you could probably use some select 2N3904/6s or add some small ballast emitter resistors.

WRT to the resistor "matching" and "value" in Nelson's circuit, as we mentioned the sensitivity of the matching is low and only ratios matter. Instead of 1MΩ/10kΩ, one might use 100kΩ/1kΩ, or other convenient ratios depending on the desired current range and sense resistor.

We used 1% unmeasured and unmatched resistors grabbed from our old parts bin with excellent results.

Best 

[PCB.Wiz]

If one followed thru with the partial derivatives for component sensitivities, all the resistors except the sense resistor should have an output current sensitivity of at least 1/(Effective Beta) wrt the sense resistor. Effective Beta is Io/Ii of the output device type.

That's rather optimistic.
Spice says it is far worse than that, as any skew in the bridge balance results in worse PSRR, (HFE varies with voltage) and if I measure PSRR, spice says

* Input feedback resistor has a 0.5 sensitivity, unbalance that 1% and PSRR degrades to 0.5%
* Most other resistors are about 0.15, so a 1% unbalance gives ~0.15% error

That means if you want 10bit or 12bit accuracy, you will need ~0.1% resistors, or better, with good ppm specs too.

[Benta]

If one followed thru with the partial derivatives for component sensitivities, all the resistors except the sense resistor should have an output current sensitivity of at least 1/(Effective Beta) wrt the sense resistor. Effective Beta is Io/Ii of the output device type.

That's rather optimistic.
Spice says it is far worse than that, as any skew in the bridge balance results in worse PSRR, (HFE varies with voltage) and if I measure PSRR, spice says

* Input feedback resistor has a 0.5 sensitivity, unbalance that 1% and PSRR degrades to 0.5%
* Most other resistors are about 0.15, so a 1% unbalance gives ~0.15% error

That means if you want 10bit or 12bit accuracy, you will need ~0.1% resistors, or better, with good ppm specs too.

I cannot reproduce your results.

Running sims on the circuit in my OP, and defining the sense resistor as a precision type (otherwise this exercise makes no sense) plus using a lousy BJT (MJD3055, Onsemi), I get the following results:

Nominal I_SINK = 100.02 mA
R1, R2: 10k, R3: 525k, R4: 475k, R5: 500, R6: 10. I_SINK = 100.17 mA
R1, R2: 10k, R3: 475k, R4: 525k, R5: 500, R6: 10 . I_SINK = 99.87 mA
R1, R2: 10k, R3, R4: 500k, R5: 475, R6: 10. I_SINK = 100.04 mA
R1, R2: 10k, R3, R4: 500k, R5: 525, R6: 10. I_SINK = 99.98 mA

I've seldom seen a circuit with so low sensitivity to component tolerances, it impresses the h*** out of me. The resistor ratio skews are at 5%!

The reference to H_FE vs V_CE is irrelevant, as this circuit cancels the effect of H_FE. And how PSRR comes into the discussion needs an explanation. Are you modulating V_CC while simulating?

Cheers.

PS: simulations run with ngspice in KiCAD V8.

[PCB.Wiz]

I cannot reproduce your results.

That's because you did not test PSRR

The reference to H_FE vs V_CE is irrelevant, as this circuit cancels the effect of H_FE.

In the real world, you expect good current sinks to not vary with voltage. (good PSRR or high output impedance)

So I run a real world spice test, of vary of the current sink voltage span, (2-35V) and then see how that varies, as the ideal resistors vary from ideal.
As the bridge unbalances, you expect PSRR to get worse, and indeed it does.

Here are the LTspice results

VC = 5-35V, dI(Re) = 17uA Io = 10.066343mA-10.083611mA
dI(R7) = 5nA on Io = 10.000385mA, with matched resistors (very good)
R5 +1% to 505 Ohms dI is -184nA  Io = 10.001045mA 0.01%
R2 +1% to 10.1k        dI is +151nA Io =  9.9857915mA  0.142%
R4 +1% to 505k         dI is -145nA  Io =  10.014834mA  0.148%
R3 +1% to 505k         dI is 17uA     Io = 10.051133mA  0.5%
R1 + 1% to 10.1k       dI = 345nA   Io = 10.015626mA  0.156%

[UnijunctionTransistor]

Good enough for Australia.

[Benta]

@PCB.Wiz:
interesting. I'll try to rerun the sim while sweeping the collector voltage.

[Benta]

I've now done the PSRR sweep, and I'm still impressed with this circuit.
The schematic has been modified to make a collector voltage sweep (5...35 V) of the output transistor:



The results you see in the attached table. The methodology is different from that of PCB.Wiz, as I've only varied one parameter at a time, so this is the sensitivity of output current vs. each resistor.
The sweeps all show monotonic behaviour, meaning there are no hidden current peaks or dips anywhere.
As can be seen, the circuit is completely insensitive to collector voltage variations, meaning that PSRR is (very theoretically) infinite.
But that's with using ideal resistors (0% tolerance).

I've done the sweeps changing each resistor by +/-5%; output current change is lower than 1% in all cases, giving a sensitivity of <0.2, which is a very good value.
More interesting is the PSRR sensitivity, which is below 0.1% in all cases.



In conclusion: this circuit has excellent PSRR, sorry.

PS: I haven't modelled changing R1 and R2, as only the resistor ratios are interesting here.

[joseangel]

Thank you all for the nice simulations and results report.
It's not my intention to correct anybody, simply to state the terminology, to avoid confusion,

- PSRR (Power Supply Rejection Ratio), is the variation of any parameter of interest wrt the Power Supply variations (including ripple, noise and the like). It is an important metric in many analog designs, even if you sometimes can avoid it altogether by providing very clean power rails.

- What you have been simulating above is simply the Output Impedance (Zo) of the current sink. I have always liked the way it is done with SPICE, by simply sweeping a voltage source (burden voltage) in the load. The simulations above indicate Zo in the order of 1 Megohm, which is quite nice 

[RoGeorge]

For the fun of it and to double check my idea, made a brief comparison.
With green is Carlson's compensation for Ib, with yellow is mine.   



CMRR with frequency of Vx (-CMRR is Zout, because the chosen AC stimulus was Vx=1V).



Transient response for a Vx swing between 5-25V, at 4 different CC values requested:  1mA, 10mA, 100mA, 1A


Changed mine a little from my previous pencil draft, by subtracting the Ib from Ie, such that the current through the R sense is kept the same as Ic, and by moving the second mirror emitters below GND (to give enough Vc for Q6 when V on R9 approaches 0V).
Pros:
   - easy to integrate in an IC (no high value resistors, no laser trimmed resistors matching)
   - has bigger Z, CMRR is with about 20dB better
   - slightly faster response and more stable
Cons:
   - doesn't behave well for very small currents (could be mitigated, but in this version it needs at least 3-5mA Iout)
   - requires from the opamp double the current (could be mitigated by using mirror BJTs with area ratio other than 1:1)
   - not suitable for discrete transistors (requires matched transistors, sensitive to thermal imbalance in the mirror BJTs)

 

[David Hess]

As can be seen, the circuit is completely insensitive to collector voltage variations, meaning that PSRR is (very theoretically) infinite.
But that's with using ideal resistors (0% tolerance).

The limited output impedance of the transistor causes a variation in Vbe which is divided by the open loop gain to create an input offset error limiting PSRR.  I think it simplifies to the output impedance of the transistor multiplied by the open loop gain, so high, but probably megohms.

[thermistor-guy]

Current sinks with BJT output always have the problem that the base current also flows into the sense resistor on the emitter. For small signal sinks normally not a problem, but power BJTs have low H_FE, which poses a problem for high precision sinks.

I found this little gem of a circuit that solves the problem with a couple of resistors. Hats off to whoever devised it, it's brilliant...

Interesting.

I once did a driver circuit for a high-power LED in a biomedical fluorescence instrument. The circuit was very much like this, except:

* no positive feedback (no R3);
* added a capacitor immediately in series with R4, for minimum DC error and for rise/fall ramp control;
* mosfet for Q1.

It went into production and worked quite well. I didn't consider trying it with BJTs (no time; hurry, on to the next thing).

[peter-h]

Yes; if you use a MOSFET then it becomes trivial. I use such a circuit in production to sink 0-20mA (for 4-20mA sensor emulation).

Interesting comments about old 3N3055 SOA. I used to work in another field where SOA was a big concern; in those days RCA had a big range of bipolar transistors, and I still have the ~1972 data book. I am amazed that SOA is a problem when you can get such huge MOSFETs.

Thinking about this some more, this approach resembles feedforward compensation for load regulation, where feedback is not desirable e.g. high voltage power supplies where you want say 1% load regulation but not 0.01%, and you don't want 50kV-capable feedback resistors. You can achieve 1% by measuring the supply current to the oscillator which drives the multiplier stack and applying some % of that to the oscillator supply voltage. As noted above, for stability the feedforward fraction needs to be small. I was doing this in a previous life, in the 1970s.

[David Hess]

Interesting comments about old 3N3055 SOA. I used to work in another field where SOA was a big concern; in those days RCA had a big range of bipolar transistors, and I still have the ~1972 data book. I am amazed that SOA is a problem when you can get such huge MOSFETs.

It becomes a cost and sometimes performance issue; larger MOSFETs are more expensive and have more capacitance limiting speed.

Early power MOSFETs were lateral parts and had square SOAs, and lower capacitance as well making them faster.  They were quickly replaced with vertical parts with smaller die but the same voltage and current ratings.

A transistor can always be derated to avoid exceeding safe-operating-area, but doing this increases cost.  In some cases, multiple devices will have to be used in series and/or parallel.

[incf]

In series? huh... In parallel I've seen and done, but never in series.

[David Hess]

In series? huh... In parallel I've seen and done, but never in series.

When dealing with non-square safe-operating-area, it can be more effective to operate two transistors in series rather than in parallel.  At  some lower voltage, somewhere between 15 and 30 volts depending on the transistor, the safe-operating-area becomes square.

[EEVblog]

Sweet circuit! 

[peter-h]

You can have transistors in series but it needs more components because you need to not only drive them all but also ensure the total voltage is divided across them fairly evenly.