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Precision Load Cell (Wheatstone Bridge) Simulator

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hozone:
Hello,

it works.
I can not say more than this cause I've not precision instruments to test it against.
Latest version has 0.0mV output, and a dip setting to allow selection of calibration Resistor or calibration Trimmer or a parallel between those.
I'll post project files later on my blog and I will link here details.

floxia:
Awesome job, please post your blog link when ready!!

hozone:
Update.
I've notice that the output has a little offset, that depends on Vexc.
On 3 out of 5 device I've found an offset of 0.29mV with 10V excitation, and 0.14mV with 5V excitation. That seems related. I can read the offset even on 0.0mV range output.
Find attached the Excel with test on 3 devices.
LTSpice simulation of course does not have this offset.
Where do you think this offset comes from?

Measured using AN870. (Even on UT-61e there's this offset).

hozone:
Update 2.
It may help.
The resistance between SIG- and SIG+ is almost 350ohm when no Excitation is provider. As soon as the Excitation is provided it change from range to range up to 470ohm almost on the 2.0mV/Vexc range.
Maybe something related to the PCB design?

hozone:
I haven't find the reason why this happens, maybe @Kleinstein can help me?

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