High-speed differential pair routing questions

[HwAoRrDk]

For high-speed differential pair routing (e.g. PCIe, SATA, etc.) where the pair has to transition to another layer using vias, I see advice that you should suppress the via pads/rings on any internal layers. For example, if the pair is going from top layer to bottom layer on a 4-layer board, you should suppress the rings on the vias on internal layers 2 and 3 (so that the via is a straight 'tube').

I ask because my PCB software (DipTrace) doesn't have the facility to do this. For some bizarre reason it allows you to do so for static, manually-placed vias, but not for automatic vias that are part of traces.

Also, I see advice to void any copper areas two layers deep beneath any AC-coupling parts. How important is this? I can do this, but I'll have to lay out the voided areas manually.

[fourtytwo42]

At the end of the day it's down to the size of the eye at the receiver and that is down to quality of the artwork vs speed and distance neither of which you have quantified ?

[Alex Eisenhut]

Just ask the PCB fabricator to remove unused inner pads.

[T3sl4co1l]

Normally it is done automatically on Gerber generation.  Check the outputs.  If still present, ask the fab to remove them -- the cheaper fabs may even do this automatically without notification(!).

I don't understand the last comment; "void" what, in what way? What are "AC-coupling parts"?  In any case, the idea of removing ground underneath traces or parts is generally not a good idea.

To understand, you need to think in terms of transmission lines and reference planes.  A signal trace over a plane has some impedance depending on trace width and height above plane.

The plane provides shielding, reducing coupling to free fields; the loop area between trace and plane is determined by height above plane, and reducing this area reduces magnetic field exposure.  Likewise reducing exposed (top visible) area, trace width, reduces electric field exposure.  Both fields together (in the right place and phase) gives far-field radiation coupling.

Wrap-around plane -- coax or stripline -- is best for minimal coupling.  Microstrip, with one side open to space, gives a little bit of coupling.  You can make antennas this way; the coupling is generally pretty low, so that a large resonant ratio is needed.  Patch antennas expose more E-field, and make practical antennas.  Most microstrip applications (say LVCMOS up to 100MHz, LVDS into the Gbps), the coupling is low enough to pass commercial emissions levels without additional shielding, just bare board in plastic enclosure sort of thing.

Opening ground beneath a trace, removes that shielding.  If there's still plane on the far side [of the hole], stitched with vias around the perimeter, then it acts as changing the substrate height for that section, and Zo increases.  If not, Zo increases even more (geometry looks more like a trace in a slotline) and radiation is significant around the resonant frequencies of the slot (folded dipole or slot antenna geometry).

The main place you might remove ground under a net, is to reduce stray capacitance for an op-amp summing node.  Higher Zo means lower C and higher L.

Everywhere else, the reduced inductance or consistent impedance is usually the higher priority, and a solid plane is desired.

Tim

[HwAoRrDk]

I don't understand the last comment; "void" what, in what way? What are "AC-coupling parts"?

Series AC-coupling caps in the TX and RX pairs of high-speed differential signalling like used in PCIe or SATA.

By voiding, I mean putting a cutout in the reference plane underneath the AC-coupling capacitor, of an area roughly equal to the size of the whole capacitor, such that it covers both pads and the gap in-between.

Apparently, it's supposed to eliminate the parasitic capacitance between the body of the cap and the reference plane, so as not to affect the impedance and avoid reflections.

[T3sl4co1l]

Oh yeah, that. For PCIe specifically, as it is AC coupled.  Or occasionally Ethernet, when done on a backplane (instead of using transformers).  But Ethernet doesn't go nearly fast enough to matter.

Note that component pads and the body itself are just more conductive material, and if they're wider than the nominal trace width (at desired Zo and substrate height), the impedance will be lower as well.

The impedance disturbance only matters in relation to the length of the disturbance, relative to the edge rate of the signal.  PCIe devices at lower bitrates won't care about an 0603, probably 0805 either, in the way.  And 0402 is easy enough to use.  For low substrate height (thin trace width), and the highest speeds, relieving ground under the part may be needed.

Tim

[HwAoRrDk]

I checked Gerber output. Alas, the rings on the vias are not automatically removed.

Somehow I doubt the likes of JLCPCB, PCBWay, etc. will acquiesce to a request to manually change dozens of vias to remove the rings for me. I'm sure a more traditional PCB fabricator would do so if asked, but I don't use them for hobby projects for obvious reasons.

Is it worth pursuing some alternate solution? (Perhaps I could edit the Gerbers manually.) Or is the difference negligible for some use-cases? I'm looking at max PCIe gen 2 (5 Gbit/s) and SATA 3.0 (6 Gbit/s).

The impedance disturbance only matters in relation to the length of the disturbance, relative to the edge rate of the signal.  PCIe devices at lower bitrates won't care about an 0603, probably 0805 either, in the way.  And 0402 is easy enough to use.  For low substrate height (thin trace width), and the highest speeds, relieving ground under the part may be needed.

What qualifies as a "lower bitrate"? According to the advice here, "At 2.5 Gb/s per lane I think you are just on the cusp of having to worry about this problem". And of course PCIe gen 2 is twice that speed. I was going to use 0603 capacitors.

[T3sl4co1l]

That sounds within expectation.  Yes, "lower bitrate" would be PCIe v.1.

I'm not sure where HoJo gets the idea that's some kind of Miller effect [between component bodies], but I guess that's par for the course; I've read very little of his work as it happens, but have heard it's rather impenetrable or mysterious at times.  Perhaps this is a microcosm of that.

I think you underestimate the amount of automation the likes of JLC etc. have in their toolchain.

...Also, how will you know?  Will the link simply work, or not?  Do you have any way to test it under timing variation, voltage, interference...?  Can you measure the eye diagram?  Will you be qualifying for compliance?  Will you inspect the board, e.g. x-ray to examine pad stack density, board sectioning to measure copper visually?

If not, just don't sweat it.  It works or it doesn't, it's a 50/50 right?

Tim

[ejeffrey]

It also depends on your stackup.  A 14 layer board with 75 micron dielectric on the outer layer is going to be a lot more sensitive to the body shunt capacitance than a 4 layer board with 360 um outer dielectric.  Advice to cut away the ground plane without specifying the stackup and component size needs to be interpreted carefully at best.

I would typically use 0402 capacitors and not worry about it.  It's definitely harder to hand assemble than 0603, but still not too bad.

[langwadt]

I checked Gerber output. Alas, the rings on the vias are not automatically removed.

Somehow I doubt the likes of JLCPCB, PCBWay, etc. will acquiesce to a request to manually change dozens of vias to remove the rings for me. I'm sure a more traditional PCB fabricator would do so if asked, but I don't use them for hobby projects for obvious reasons.

you said your SW supports removing non-functional pads on manually places vias, so just replace the automatic vias with manual ones once you are done routing?
shouldn't be that many

[mariahcarey]

For high-speed differential pair routing (e.g. PCIe, SATA, etc.) where the pair has to transition to another layer using vias, I see advice that you should suppress the via pads/rings on any internal layers. For example, if the pair is going from top layer to bottom layer on a 4-layer board, you should suppress the rings on the vias on internal layers 2 and 3 (so that the via is a straight 'tube').mapquest

I ask because my PCB software (DipTrace) doesn't have the facility to do this. For some bizarre reason it allows you to do so for static, manually-placed vias, but not for automatic vias that are part of traces.

Also, I see advice to void any copper areas two layers deep beneath any AC-coupling parts. How important is this? I can do this, but I'll have to lay out the voided areas manually.

While it's ideal to suppress the via pads/rings, especially for high-speed signals like PCIe and SATA, the absence of this feature in your PCB software doesn't necessarily mean you can't achieve good signal integrity. You can still design high-quality vias with minimal pad sizes and carefully control the via aspect ratio to minimize signal disruptions. Additionally, ensure that the via placement and routing adhere to best practices for impedance matching and signal integrity, such as maintaining controlled impedance traces and minimizing signal transitions.

[selcuk]

JLCPCB removed that unconnected rings from the Inner1 & Inner2 layer gerber files of my recent 4-layer design. I didn't ask or expect and I saw it while comparing the manufacturing gerbers with mines. I thought that this was a routine job for them. If it is important, you can mark the option for gerber approval while ordering.