EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: Warhawk on September 26, 2018, 11:15:46 am
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Hi everyone, I am working on a project which requires a precision voltage clamp (aka clipper, limiter) with the variable limit, ideally from 0 to 3.3 V. I can't use the popular solution (https://i.stack.imgur.com/xAzPB.png) based on a single opamp and a diode because I don't have any negative supply in the system. For this reason, I came up with a circuit which uses a single supply opamp driving an NMOS transistor. Benefits are that I don't need the negative supply for the opamp and the opamp also saturates to the negative instead of to the positive rail which makes it theoretically faster because of the slew-rate limitation.
This circuit seems to be working but it is extremely difficult to make it stable. I mean, it is difficult for me. I am hoping that some analog gurus here could give me a hint and brainstorm how to improve the circuit. I am thinking about an anti-saturation circuit but first of all, I would like to get recommendations on how to address stability concerns properly.
Attached are a printscreen and LTspice files.
Many thanks, Jiri
edit: The opamp model exhibits high input bias current during negative saturation. Not sure whether this is just a bug in the model or ESD somehow kicks in. nevertheless, this causes the slight bumb at 2.5V.
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I would first reduce the value of R1 to 100R and then see what effect C1 has on stability and transient response. R1 & R2 in combination with the gate capacitances of the FET creates a pole and subsequent delay or phase shift. This capacitance will be greater than that shown on the FET data sheet due to the voltage gain and the reverse transfer capacitance of the FET - see Miller Effect.
Op-amps are not always stable when driving a large capacitive load so a larger value of R1 can help, BUT FETs can have spurious oscillations if the gate resistor is too large. Try varying the value of R1 to see what happens. Note that Spice will probably not predict these oscillations.
Cheers,
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How much precision do you want? 10s of microvolts? A couple millivolts?
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How much precision do you want? 10s of microvolts? A couple millivolts?
I am sorry it took me long to reply. Accuracy is not as important as transient response. A couple milivolts sounds about right.
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I would first reduce the value of R1 to 100R and then see what effect C1 has on stability and transient response. R1 & R2 in combination with the gate capacitances of the FET creates a pole and subsequent delay or phase shift. This capacitance will be greater than that shown on the FET data sheet due to the voltage gain and the reverse transfer capacitance of the FET - see Miller Effect.
Op-amps are not always stable when driving a large capacitive load so a larger value of R1 can help, BUT FETs can have spurious oscillations if the gate resistor is too large. Try varying the value of R1 to see what happens. Note that Spice will probably not predict these oscillations.
Cheers,
Good Idea, I did not realize this before. I'll check. Additionally, I want to build a real circuit before implementing it into the system.
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A couple of comments to explain features in your simulation:
1) As you noted, the 2.5V clamp level has a slight hump which you identified with increased input bias current.
That is sort of correct. If you look at the OPAx172 data sheet, you'll notice that there are diodes between the 2 inputs. It would appear you are seeing current sourced from your Vctrl source through one of the diodes. As Vctrl gets above vin by a diode, there will be a 1/11 gain to vout.
2) The delayed clamping action as Vctrl goes below 2.5V at the end of that same section: That's happening because the opamp/NFET clamp is open circuit during this period. Thus, the opamp is behaving as a basic integrator (its own local loop is a closed circuit) with the vin source as the + reference input of the opamp. The downward ramp of Vctrl ramps between 2.5V and ~2.25V while vout doesn't change (meaning the opamp/NFET clamp circuit is open loop). Whats happening is that the 10k resistor is a V->I converter. The current is given by (Vctrl(t) - 2.5V)/10k. Since this is linear over time, we can say Vctrl(t) is 2.375V on average. That means the average current in question is (2.375V - 2.5V)/10k = -12.5uA. The output of the opamp is 0V at the beginning (Vctrl has been higher than 2.5V for a period of time, so the output of the opamp will have integrated to 0V). The -12.5uA will charge the 22pF cap from 0V on the output node at a rate given by the standard I = C*(dV/dt) relationship. This makes dV/dt = I/C = 12.5u/22p = 0.57V/us. If the NFET has a threshold of about 2V - 2.5V, there will be a period of 4-5 us until the opamp/NFET clamp becomes closed circuit and the clamp is active. That looks about right from the graph.
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How much precision do you want? 10s of microvolts? A couple millivolts?
I am sorry it took me long to reply. Accuracy is not as important as transient response. A couple millivolts sounds about right.
How fast does the transient response need to be then?
The fastest way is to use a current driven diode bridge driven from a voltage source with a resistive load and buffer on the output. The currents into the diode bridge set the low and high clamp levels. For a single supply application, only the top or bottom half of the diode bridge is needed and a single current. The offset voltage is determined by the matching of the diode forward voltage drops. Open loop peak detectors work the same way.
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How fast does the transient response need to be then?
I am hoping for ~20us reaction time which should be feasible.
The fastest way is to use a current driven diode bridge driven from a voltage source with a resistive load and buffer on the output. The currents into the diode bridge set the low and high clamp levels. For a single supply application, only the top or bottom half of the diode bridge is needed and a single current. The offset voltage is determined by the matching of the diode forward voltage drops. Open loop peak detectors work the same way.
I've just came across this (https://www.eevblog.com/forum/projects/limiting-op-amp-output/50/) thread. I get your point with diodes but it still requires a negative voltage supply which I am trying to avoid as much as I can.
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Guys,
I may have found an elegant solution with just a few components and no diodes :) What do you think about it?
The circuit uses two difference amplifiers. The first one measures the difference between the reference voltage (limit) and signal amplitude. The second difference amplifier subtracts the difference. The drawback of single-ended power supply now works as a benefit - the circuit works only in one polarity and I don't need a diode.
I am quite happy about it. What do I miss? ::)
PS: Yes, R1+R3 are redundant to R5+R7. It makes the circuit just easier to read.
Note: I have a spare opamp in the design and I needed a buffer for my previous circuit anyway. :-+