i tried some 40107 (simulations). it seems almost anything with capability to handle a large sink and momentary short can be a nice driver. but then again, im just mucking around with mosfets
From a 5V supply, CD40107 has an equivalent output resistance around 500 ohms, and switches in 200ns or so. Dreadfully slow, and weaker than American piss beer!
A simulation code model may not correctly simulate the output pin driver. Supposedly, LTSpice treats all digital logic, by default, as 1V supply. VDD, what's that?
The actual mosfet switching losses occur at the transitions. At turn on the drain voltage is collapsing and the drain current is rising. They overlap for a part of the transition. The same thing happens when the fet turns off; drain voltage rises and drain current collapses the overlap occurs again. That can cause high peak power losses depending on the voltages and currents involved. The average power losses increase with switching frequency it can be more then conduction losses.
If one assumes the current rises linearly, then the voltage falls linearly (typical of an inductive hard switching turn-on event), and vice versa (inductive turn-off), the power dissipation will spike in a triangle shape, of width T1+T2 (where T1 and T2 are the rise/fall times of current and voltage, respectively), a peak power of Vcc * Isw, and thus a total energy of 0.5 * Vcc * Isw * (T1+T2). Quick example: a buck converter, CCM, 100V input, 10A output. If the switching takes 100ns, the energy per edge is 0.5 * 100V * 10A * 0.1us = 50uJ. The total per cycle, of course, is simply double, or 100uJ. At 100kHz, this is 100u * 0.1M = 10W average, or P = Tsw * Vcc * Isw * F.
Note that Tsw = T1 + T2 is NOT the risetime of a given waveform in the circuit. If you measure only the drain voltage, you are getting literally half the story.
The same waveform is typical of capacitive loads as well, though these are uncommon in switching power supplies. A pure resistive load has voltage falling, while current is rising, proportionally, and therefore has a quadratic power waveform, with a peak power of Vcc * Isw / 4, and an enclosed area (energy) of Vcc * Isw * Tsw / 6 (a dash of calculus proves the /6).
With a snubber, or resonant or quasi-resonant design, the switching losses can be considerably different, because the voltage and current are no longer inductive at all times.
For say a higher voltage application output (drain) capacitance can be a source of significant losses.
Not really; in fact, your example illustrates this better than merely showing the magnitude of capacitive losses. The comparison is this:
Your 24W switcher might dissipate 400V * 1.1A[note1] * 0.5 * 0.05us[note2] * 0.1 MHz = 2.2W in switching losses.
Note the 0.5 is back, because the flyback is probably doing most of the switching losses during turn-off. Note also that 400V is the flyback waveform peak, not "Vcc"; this is the correct equivalent to the buck example's Vcc.
[note1] You didn't mention peak current; assuming a maximum 50% duty cycle in DCM, 0.448A RMS is 1.1A peak.
[note2] You also didn't mention switching time, so I'm making a SWAG. Often, that's about the best you can do without actually building and measuring the thing, anyway. So, the resulting number is of course proportionally uncertain.
Even if Tsw is vastly shorter (it can't be too much shorter; Rg is specified as 16 ohms on that device, so you shouldn't gain more than fourfold or so with an ideal gate driver), it's still more than the estimated conduction (0.16W) and capacitive (0.27W) losses.
In higher voltage mosfet you will see Eoss expressed in uJ usually at 400V. That is the energy in the drain capacitance at 400V. To convert energy to power multiply times frequency.
Beware that many devices do not specify Eoss. One
cannot use Coss to estimate Eoss, because Coss is measured at one voltage only! It varies extremely strongly with bias voltage (the AOD11S60 datasheet being a prime example of modern "super junction" transistors, which are more nonlinear than ever!)...
ok ima use a MOSFET BUK9Y59-60E for testing my math 
, ima switch this @ 13Mhz (assuming peak current @ 10A, peak voltage @ 50volts)
http://www.farnell.com/datasheets/1705534.pdf
Coss 66pF = 82.5nJ (@50v)
...So as you can see, a mistake which can easily be made
See [BUK9Y59] Fig.15. Do you think a capacitor that varies like that will actually absorb 82nJ worth of energy? Is it more, is it less? What is it really? Hard to say, without a spec in the datasheet, and without doing calculus on the graph (bah!). Fortunately it's small enough to ignore, for the most part.
btw what about avalanche charge? how does this parameter apply to designs?
and looking at fig 15, t1 +T2 = T_fall ? or its somewhat in the early part of T3?
What are you looking at? Neither of the datasheets referenced mention those terms? Anyway, avalanche is about excessive voltage causing breakdown. Which can damage the transistor in spots if it occurs quickly, or thermal failure if it occurs more slowly (which is why they say "single pulse" or whatever, and specify what temperature the transistor was at to start with). Manufacturers almost always provide the second kind, because the number looks better, while the first kind generally beguiles the unprepared switcher novice.
Tim
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