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Electronics => Projects, Designs, and Technical Stuff => Topic started by: Bud on March 09, 2016, 08:18:34 pm

Title: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:18:34 pm
Part 1. Preface

This write-up was inspired by an earlier discussion about rigol DS1000Z series oscilloscopes, when a problem was discovered with the master clock oscillator in that line of scopes. The problem was caused by incorrectly selected PLL (phase locked loop) component values and strange programming of the PLL chip that could not be reasonably explained. Details can be found starting from this post by MarkL here:

https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777 (https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777)

Basically, the PLL was wobbly instead of outputting a stable clock signal. Because the clock drove the ADC chip, the jitter was directly affecting the ADC sampling. MarkL took a few screenshots of the PLL spectrum using his spectrum analyzer and the clock looked plain awful. There was no explanation or justification to such poor PLL clock design other than incompetency of the scope manufacturer and lack or absence of quality control on their production line. 

The manufacturer then issued a firmware update that bandaged the problem but did not eliminate it entirely, partially because a proper update required changing the hardware – the PLL loop components on the PCB. The second reason was of the same nature as the one I discovered during this project, and also required replacing the hardware components – more information on this will be provided later in this article.

After that and being still puzzled by the foolishness of this problem in DS1000Z scopes I decided to check  my DS2072A scope. I am sure you’ve already guessed what I found. The answer is yes, same problem with the PLL clock existed in DS2072A. The 1GHz PLL clock was modulated like hell and sometime failed completely, generating plain narrow band noise. I decided to check it a little bit more and see if I can fix the PLL. At the time I did not realize this will become such a sizable investigation which I eventually named the “Project Yaigol”.

During my investigation I observed (and you will see it for yourself as you read) that the manufacturer of these scopes could not make oscillate the circuits that should oscillate, but was very successful in making oscillate circuits that should not oscillate. For that reason I called that company “the masters of reverse oscillation”. To integrate this honorable title into their name, the R letter was flipped. The backwards R is written as “Ya” and pronounced  “ja” as in yacht or yack. Hence the name of the project: “Project Yaigol”.  ;)

In this article I will provide information to DS2000 scope owners how to fix the PLL and how to fix other not less ridiculous problems I found during the investigation. Same as I, you may not at first believe such stupidity can happen. The bad news for you is the problems are caused by fundamental reasons, i.e. not by component tolerances but by bad design decisions as well as by programming that is incoherent with the underlying hardware. The good news is that not much effort is required to perform the fix. Still, it involves SMT work so you have to have appropriate skills and tools to do it. I will be giving instruction in the article as I write and I will summarize it all together in the end, so If you do not want to read the complete article you can jump straight to the last part for a fix guide.

I began looking into it somewhere in April 2015 and it lasted until late June, making notes and taking screenshots. This information has been sitting and waiting since then but I kept postponing writing a post because of other things. I will see if I can do it now and I am going to break it to parts organized by topics. Still may take a couple weeks to complete so please bear with me. Hope this will be to you both entertaining and useful.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:20:17 pm
Part 2. The PLL

Please use the attached PDFs. I had to split to two files because of attachment size restrictions. I may convert to HTML for online read when have time.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:23:10 pm
Part 3. The PLL Power Supply

Please use the attached PDF
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:24:31 pm
Part 4. Other Power Supplies

Please use the attached PDF.

Additional artefacts are here:
https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg897887/#msg897887 (https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg897887/#msg897887)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:26:34 pm
Part 5. Front End performance

This part deals with the input stage of the scope, i.e. signal path from the BNC jack on the front panel through to the ADC input. Information presented here may be useful for troubleshooting/repair or learning. There is no design errors fixing in this part.

The two scope channels are identical, this is a photo of one channel:

DS2072A_input_stage.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=210713;image)

The input BNC jack is at the bottom, together with a relay that connects a 50 Ohm terminating resistor and the resistor itself. The signal travels up through two attenuator stages, passes through a FET transistor buffer, a variable gain amplifier IC with switchable bandwidth in the top part  of the photo and exits on the top left via an ADC differential buffer IC. The signal then is routed straight to the ADC input pins.

Same as with the PLL chip, Yaigol made another foolish attempt to disguise the IC part numbers by lasering them off. But EEVBlog is here to uncovers these secrets for you. The VGA with controllable bandwidth is Texas Instruments LMH6518 (http://www.ti.com/lit/ds/symlink/lmh6518.pdf) 900 MHz, Digitally Controlled, Variable Gain Amplifier, and the ADC driver is LMH6552 (http://www.ti.com/lit/ds/symlink/lmh6552.pdf) 1.5-GHz Fully Differential Amplifier from the same company.

Gain_stage.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=210715;image)

DS2072A can switch input impedance between 50 Ohm and high impedance. However it also has a stupid bug causing the scope forget it was on 50 Ohm between power ups. You work with an RF circuit, you turn 50 Ohm input On, do you stuff, power off the scope for the night, come back couple days later, power it on, measure your circuit again and ...  :wtf:  the ends do not meet. Perhaps need to turn 50 Ohm termination? You go to settings, hmmm....  it shows 50 Ohm is On   :-//  , unless you realize you need to cycle the setting to get 50 Ohm termination back.  :rant:  The stupid thing tells you it is on 50 Ohm whereas in fact it is not. I have not tested if the bug was fixed in the last firmware. It was not obvious in the earlier firmware either, I could not understand a pattern how/when that happened, it did not happen every time.

The following is a VNA screenshot of input impedance on 50 Ohm setting, Yaigol vs Tektronix 2467B 400MHz analog scope. Yaigol traces are red/green, Tek is blue/yellow. Above 100MHz Tek has a better 50 Ohm compliance.

S11 Yaigol vs Tek.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=210717;image)

The following is a VNA screenshot of Yaigol on High Impedance setting. Input impedance is capacitive with Cin about 18.5pF.

S11 Yaigol high impedance.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=210719;image)

The attenuator has two stages, a reverse engineered schematic is provided below. I cannot guarantee 100% correctness, I did not try very hard, but it gives you an idea about the overall topology.

DS2072A attenuator.gif
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=210721;image)

Parts annotation in the schematic is arbitrary. I captured the resistor values but did not measure the capacitors. The topology has quite a few frequency dependent correction circuits but if eliminate them, a equivalent schematic at DC can be composed, which was presented in the above picture.
The first stage appears to have 8dB voltage attenuation, the second stage 16dB, which I calculated based on actual in-circuit measurements of a signal passing through the stages - the test conditions are indicated in the above picture at the bottom.

In terms of power the attenuators present 16dB and 32dB attenuation stages, with 48dB of power attenuation when both attenuators are engaged. Interestingly, the overall attenuation of the input stage from input jack to the output of the VGA LMH6518 measured at its output is 32dB. The following VNA screenshot shows attenuation level with both attenuators engaged relative to attenuators turned off. It can be seen that total attenuation of the signal path is about 33dB.

BW limit off with attenuator relative dB.gif
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=210723;image)

So how come the total loss of the two attenuators is 48dB but we measured only 32dB at VGA output? Apparently the VGA compensates for the missing 16dB loss. This may be kind of stupid, why attenuate and then compensate by amplifying. My guess it is a compromise to have an input stage with wide range of V/Div settings. The VGA chip itself has a variable attenuator and static gain blocks - refer to Fig.57 in the Datasheet. Page 21 of the Datasheet explains how it works together to build a oscilloscope input front-end.

The next stage after the attenuator is DC/AC coupling control circuit (Y214S electronic relay) and the signal splits to AC path via a capacitor and DC path via an IC (that seems to be AD8510) that mixes it with the vertical offset control voltage (bottom part of the following schematic). The composite signal then enters the JFET high impedance buffer. The first stage of the buffer is a JFET N-channel transistor, the second stage is a NPN emitter follower. The buffer topology boils down to two current sink loaded stages shown in the right part of the schematic (you The Art of Electronics aficionados feel free to correct me if I got it wrong).

DS2072A JFET Buffer.gif
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=211931;image)

The JFET buffer output is wired to the next stage which performs input conditioning magic, i.e. some of amplification/attenuation and the bandwidth control. It is built on TI LMH6518 variable gain amplifier (a link to the datasheet was provided above). This is where your "enhanced" bandwidth lives. It is also the biggest noise generator out of everything else in the analog signal path.

Gain and bandwidth of LMH6518 amplifier is controlled via SPI bus. Gain settings depend on selected V/Div and input attenuator section. The IC provides selectable bandwidth of 20,100,200,350,650,750 and 900 MHz. In Yaigol DS2000 series scopes I guess the first 3 settings are used. So the little beast is capable of some more. I believe this stage also have feeds from the system processor for offset calibration. The amplifier converts single ended input into a differential output and is followed by the ADC buffer amplifier LMH6552 with voltage gain of 2.

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=211933;image)

Measured bandwidth at the output of bandwidth controlled LMH6518 is shown next, with the 3 bandwidth settings marked. This is a composite image made from 3 separate  measurements with the scope set to 20MHz, 100MHz and Full bandwidth (note we are looking at the hacked scope). The roll-off in the left part of the chart below 3MHz was caused by roll-off of the balun used to take bandwidth measurements and should be ignored.

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=211935;image)

The 100MHz and Full are not exactly 100MHz and 300MHz, but the ADC driver buffer seems to compensate for it. The following image shows the measured bandwidth of the ADC buffer alone and the combined bandwidth. The overall 3dB bandwidth of the input stage seems to be in the area of 350MHz.

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=211937;image)

The output of the ADC driver IC goes to the ADC chip via two 47.9 Ohm series resistors.
This completes Part 5 and in Part 6 we will take a look at the ADC.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:28:06 pm
Part 6.  ADC performance

Reserved for future updates

For now take look at this post:
https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg907254/#msg907254 (https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg907254/#msg907254)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:29:16 pm
Part 7. Thermal profile

This section has a few thermal pictures taken with my modified FLIR E4 thermal imaging camera.
The hottest area on the board is the ADC and its surroundings, also spreading to the front end under the shielding can as can be seen in the following pictures:

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208843;image)

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208845;image)

The ADS chip runs hot, as well as its AVDD voltage regulator:

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208847;image)


And even the cooling fan itself is kind of warm:

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208871;image)

I also made a few panoramic shots. I had no a proper tripod camera holder attachment, so please excise my crude setup:

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208849;image)

It was pain in the butt to make panoramic radiometric pictures from a series of 320x240 shots. I recall I had to combine 8 of them to make one panoramic picture. There were posts in Flir E4 teardown thread and others about procedures and tools but in general it was painful and today I even cant remember what I did and how I did it. But once panoramic radiometric pics were complete it was fun to play with them.

I was feeling bad for the poor ADC fellow, so I fitted a lightweight heatsink I got from Digikey on it. The heatsink came with acrylic adhesive, so no mounting hardware was needed. That dropped the ADC temperature by about 20 degrees C. Here is a few shots before and after installing the ADC heatsink.

no_heatsink.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208851;image)

with_heatsink.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208853;image)

Same but  loaded into FLIR Tools software and with measurements over the hottest spots, which were the ADC, its AVDD NCP1117 LDO voltage regulator to the right of it, and the analog front end -5V LDO voltage regulator in the bottom part of the pictures. Wit no heatsink the ADC ran at 84C. With one the ADC temperature dropped to 62C or something, see the cursor measurements on the right side of the screenshots:

flir_no_heatsink.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208867;image)

flir_with_heatsink.jpg
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208869;image)

Some of the attached to this post files are the radiometric files (files with "rad" in their filename). If you have radiometric software you can load and play with measurements and palettes.
I will post radiometric version of the above panoramic files separately because of attachment size restrictions.

I think putting a heatsink on the ADC would allow replacing the fan with a quieter model. A quieter fan would almost certainly produce less CFM volume air flow which I think a heatsink could help compensate by more effective dissipation of heat from the ADC. There were complains elsewhere on this forum the DS2000 fan is uncomfortably loud. I did not have a problem with that as I have much more noisy equipment in my Lab, but anyway, just sharing my thoughts.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 09, 2016, 08:30:23 pm
Part 8.  Getting it right.

FLIR radiometric files of DS2072A board are attached.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 10, 2016, 08:05:28 pm
Subscribed
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: EV on March 10, 2016, 08:27:32 pm
Subscribed

+1
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: crispy_tofu on March 10, 2016, 09:06:00 pm
++1
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: veryevil on March 10, 2016, 11:17:00 pm
Just bought a ds1054z yesterday!  Subscribed
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rigrunner on March 11, 2016, 12:51:04 am
Subscribed
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: borjam on March 11, 2016, 12:54:23 am
Subscribed, got a 1074Z a couple of weeks ago :)

 :popcorn: :popcorn:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Siwastaja on March 11, 2016, 12:55:09 am
Ignored thread due to idiots "+1!!!!!11!!1" bumping it one by one so you always get your hopes high that there is some new content here  :palm:  :palm:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AlessandroAU on March 11, 2016, 03:20:33 am
Can't wait for this. Really hampers using the scope for large ffts with the current pll
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tino_so on March 11, 2016, 02:56:41 pm
Looking forward to reading this saga  :popcorn: 

Regards,
Yaigol user.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on March 12, 2016, 06:33:48 am
Thanks for investigating this and collecting all the info. Looking forward to the upcoming posts. :-/O
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 12, 2016, 08:47:32 am
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 12, 2016, 11:48:38 am
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
And who learns anything from that thinking?  :palm:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wguibas on March 12, 2016, 12:29:32 pm
I agree, tell us the fixes, so we can use them.  I think I'll still learn the lesson.  The suspense is killing me :palm: :palm:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on March 12, 2016, 02:17:21 pm
Patience, grasshoppers. Patience. ;D
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 14, 2016, 01:42:56 am
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
And who learns anything from that thinking?  :palm:
You want to assemble your own car? Build your own oscilloscope? At some point you just have to take things for granted and move on to more interesting challenges. Besides that I'm quite sure the fix in itself will explain what is wrong with the PLL design.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: miguelvp on March 14, 2016, 06:03:47 am
I'm looking forward this constructive criticism.
Even for those that won't modify their scope, they will learn the limitations of their test equipment in comparison to the modified one.

win/win  :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 14, 2016, 09:13:07 am
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
And who learns anything from that thinking?  :palm:
You want to assemble your own car? Build your own oscilloscope? At some point you just have to take things for granted and move on to more interesting challenges. Besides that I'm quite sure the fix in itself will explain what is wrong with the PLL design.
Agreed, a scope is a tool for developing other circuits, not necessarily a thing that everyone needs to study in its own right.

Not every dragon slayer also needs to be a blacksmith, even though they might benefit from a sharper sword.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nanofrog on March 14, 2016, 10:46:54 am
Sounds like this took quite a bit of work Bud, so I'd like to say thanks for your investigation and posting the results in advance.  :-+

Looking forward to following the thread as it develops.  :)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 14, 2016, 07:04:44 pm
Yes it took a while and unfortunately takes long to get the info to you guys. Sorry.
Just updated Part 2, you can start reading.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Wirehead on March 14, 2016, 07:11:24 pm
Yes it took a while and unfortunately takes long to get the info to you guys. Sorry.
Just updated Part 2, you can start reading.
Nice write-up - interesting!  :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: veryevil on March 14, 2016, 07:46:46 pm
Hi, great work.

With the test pads and the zero-ohm resistors on the bus would it not make sense to remove the resistors and fit a small micro to the bus to program the correct settings? Take the 3v3 from the NCP1117 and have it once set the freq. it could even be tied to the lock pin and monitor that as well?

Thanks again
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rigrunner on March 14, 2016, 08:13:40 pm
Thanks for posting  Bud  :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 14, 2016, 09:10:29 pm
Really a great job  :-+
Now kill the "bat"  ;)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AlessandroAU on March 14, 2016, 10:33:21 pm
Thank you so much for the time and effect that went into this. I can't wait for part 3. Very keen to get the scope working as it should.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 14, 2016, 11:07:44 pm
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!

Better to include the analysis so that people can judge the competence and validity of the statements. That will distinguish the statements from the vast majority of unsupported assertions seen on the net.

Anyone wanting to skip the analysis (and jump to conclusions) is then free to do so.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: c4757p on March 14, 2016, 11:26:13 pm
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!

I don't understand this. Clearly the analysis is something he wants to share with us, it seems he thought it was interesting and thought we might as well. I'm not sure if I'm the only one who thinks this, but this "skip the analysis" sounds very rude to me, like he did all this work and you're not willing in return to put up with the way he wants to present it...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: dr.diesel on March 14, 2016, 11:53:27 pm
Keep it up Bud, I'm enjoying the analysis as well. 
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: jh15 on March 15, 2016, 12:10:59 am
EEV forum is more of a time sink than a video game:)

Just stumbled across this thread and will try your fix after others try or fail.

Now, your wire inductors, are they at right angles? Hard to tell from picture angle. Or maybe they are far enough apart to prevent coupling?

Anyway, good stuff, read it all. I'll also have to do the 50 to 100mhz mod while I'm at it.

What about calibration, will it need a cal lab adjustment after?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 02:25:00 am
With the test pads and the zero-ohm resistors on the bus would it not make sense to remove the resistors and fit a small micro to the bus to program the correct settings? Take the 3v3 from the NCP1117 and have it once set the freq. it could even be tied to the lock pin and monitor that as well?

That is right, this can be done. In fact i considered as the final solution and i also done a lot of testing with an external PIC connected to the PLL. That way i was able to try different PLL settings. As i mentioned in Part 2, a configuration with a higher PFD frequency (i tried up to about 7MHz) produced a better clock with less phase nose (>10dB improvement), but in the end i decided to leave the factory programming because of two reasons:

- further improvement in the PLL noise would not have a material effect overall because it would be swallowed by the ADC noise which is the second biggest offender responsible for overall system noise. The first and biggest offender is the front end amplifier, i will talk about it later on in the article.

- not many users would be willing to replicate that solution. What i proposed in the article should be good enough and fairly easy to do and without cosmetically disturbing the PCB.


Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 02:37:25 am
EEV forum is more of a time sink than a video game:)
Could not say it any better  ;D

Quote
Now, your wire inductors, are they at right angles? Hard to tell from picture angle. Or maybe they are far enough apart to prevent coupling?

I ended up with them not being exactly at right angle because i tweaked them while watching the SA screen for best result (S/N ratio). Making them by hand i would not know the exact inductance value. If they were SMT parts i would mount at right angle in order to minimize change in the part's nominal inductance. The ADI datasheet formula says should be 3.18 nH so we want about 3nH assuming the other 0.2nH or something will be contributed by the ground vias.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 02:39:30 am
Now kill the "bat"  ;)

You bet, there should be a silver bullet for it
 :)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 02:45:17 am
Thank you so much for the time and effect that went into this. I can't wait for part 3. Very keen to get the scope working as it should.

Was that your software to process waveform data files and display FFT ? I did not try a offline FFT after the mod. May be someone in this thread could post Before and After pictures of an offline FFT.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hayatepilot on March 15, 2016, 02:53:13 am
Great Project!  :-+
But sad, that someone on a forum has to do the job of RIGOL...   :-BROKE
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AlessandroAU on March 15, 2016, 03:28:48 am
Thank you so much for the time and effect that went into this. I can't wait for part 3. Very keen to get the scope working as it should.

Was that your software to process waveform data files and display FFT ? I did not try a offline FFT after the mod. May be someone in this thread could post Before and After pictures of an offline FFT.

Hi bud,

I think there are 2 or 3 different projects to download the scope memory and do an FFT, one of them was mine . You can find it by looking through my post history. You need the labview RTE (it's free) to run my exe so it's a bit 'bloated' but that's the price for quick development in labview.

I am very interested in this project because cleaning up the mess that occurs in the FFT with the stock pll is a goal of mine. I would be very interested in seeing the improvements you've made to that effect.

When you release the rest of the documentation and when I get around to doing the mods on my 1054z I will definitely post a comparison FFT with the full 24mpoints. 
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 03:31:37 am
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
This is easy - just bookmark this thread and come back in a month or so and go straight to the last part.

EDIT: the fix part of it ends in Part 4, the rest is going to be exploratory information about the scope capabilities and some reverse engineering of the front end, which a curious reader may find useful.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 03:45:06 am
@AlessandroAU

Ok so i start thinking that a higher PFD solution with an external PIC could make sense for offline FFT to get to the best of its capability...

@ All:
So you guys see, if you did not read the complete document with analysis, you would not get what we may be talking about in this thread, example being this post.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nanofrog on March 15, 2016, 04:41:09 am
So you guys see, if you did not read the complete document with analysis, you would not get what we may be talking about in this thread, example being this post.
Nice work Bud, and patiently awaiting for more.  :-+

BTW, I particularly like those high-end inductors you installed in the VCO section.  >:D  :-DD Amazing at how simple a solution can be if you know what you're doing.  ;)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: ElectricGuy on March 15, 2016, 05:39:15 am
Part 2. The PLL

Please use the attached PDFs. I had to split to two files because of attachment size restrictions. I may convert to HTML for online read when have time.

I mean.... Man, what a great job you did here! Thank you!  :-+ :-+ :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 05:57:37 am
Caused me only a 3 hr sleep this morning...
 ::)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: ElectricGuy on March 15, 2016, 06:38:27 am
Caused me only a 3 hr sleep this morning...
 ::)

You should not loose time slepping!!! That's what Yagol Yngineers did!!!!

Do not sleep again, and release Part3  :popcorn:

Just Kidding, and thank you for not sleeping and present us with this great work.....
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: moffy on March 15, 2016, 11:09:26 am
Fantastic work! Also I envy your test setup, 2 spectrum analysers, wow. Can't stand the suspense though, those bat wings look awfully like low level amplitude modulation of the carrier/clock.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 15, 2016, 11:22:42 am
Bud with MarkL's assistance bought the poorly implemented Yaigol PLL clock to our attention nearly 18 months ago (for those that were taking notice), there is much about it in the previously linked thread and since then has documented the ordeal in this thread for the benefit of all.  :clap:

That he has taken so long to present his findings in detail is confusing to me and I wait with great interest for any gems not yet revealed.  :-BROKE

Carry on Bud, the floor is yours.  :popcorn:

BTW you could probably get the 2 pdfs in one post by posting one and then the other by way of a "Modify".
Not sure, but it'd be worth a try rather than have to download the 1.5 mb which will a PITA for some.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 11:52:03 am
BTW you could probably get the 2 pdfs in one post by posting one and then the other by way of a "Modify".

Sorry I am not sure I understand.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 15, 2016, 12:03:38 pm
BTW you could probably get the 2 pdfs in one post by posting one and then the other by way of a "Modify".

Sorry I am not sure I understand.
Sorry Bud if I wasn't clear, I meant having both the text and pictorial content of both pdf's in the body of reply #2  as well as being able to download it.
You'd probably have to compress all the pics to stay within forum limits but that wouldn't matter if the full size ones were available in the pdf's for download.

If you want, I'll try and then you can copy/paste into reply #2 after which I'd delete any unnecessary post/s.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Alex Eisenhut on March 15, 2016, 02:38:51 pm
Does anyone else think there should be a decoupling cap close to the power pin of the oscillator? Looks to me like there's a LC filter and a ferrite on the input of the regulator, as well as the usual big/small cap combo, but nothing on the load side. I see a little guy floating up there but not right next to the IC.
Unless the cap is on the bottom side, there seems to be vias for that there.

Granted, the thing is probably not drawing more than 10mA, but wouldn't it be best to knock out high frequency energy on the load side, rather than only on the input side of the regulator?

It might change nothing at all, but for a 1 cent part, I thought it was SOP to sprinkle power decoupling caps liberally. I mean you can always depopulate it after some empirical tweaking, no?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 04:25:06 pm
I meant having both the text and pictorial content of both pdf's in the body of reply #2  as well as being able to download it.

But you cant just post pictures in the body of a reply, you have to host them elsewhere and point picture URLs to them from your reply, haven't you?

Quote
If you want, I'll try and then you can copy/paste into reply #2 after which I'd delete any unnecessary post/s.

Sure that would be ideal, as I am not sure when I can get to creating and formatting in-reply copy of it. I can provide a MS Word source file if that helps.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 04:32:27 pm
Does anyone else think there should be a decoupling cap close to the power pin of the oscillator?

I tried one, it did not make a difference. The proper fix is in Part 3 which I just posted.

Quote
Granted, the thing is probably not drawing more than 10mA

Overall current through the LDO is 38mA, that includes the oscillator and the PLL.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 04:39:33 pm
I just found my old notes which says the home made inductors for the PLL should use 9mm long #30 wire (not 7mm as in the article). It also says I measured one made from 10mm length with the VNA and it had 3.25nH inductance at 1GHz. Seems I then reduced the length to 9mm to drop inductance a little.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: ve7xen on March 15, 2016, 04:40:10 pm
I meant having both the text and pictorial content of both pdf's in the body of reply #2  as well as being able to download it.

But you cant just post pictures in the body of a reply, you have to host them elsewhere and point picture URLs to them from your reply, haven't you?

You can attach the pictures to the post, then click 'preview' to get the URL of the attached image (this might actually appear before you click 'preview' when you're uploading attachments), then use the `[img]` tag to post them inline. A bit of a pain, but possible.

Great work in this thread!!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 15, 2016, 04:43:04 pm
Oh men, too much work attaching pictures...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 15, 2016, 05:52:58 pm
Bud with MarkL's assistance bought the poorly implemented Yaigol PLL clock to our attention nearly 18 months ago (for those that were taking notice), there is much about it in the previously linked thread and since then has documented the ordeal in this thread for the benefit of all.  :clap:

That he has taken so long to present his findings in detail is confusing to me and I wait with great interest for any gems not yet revealed.  :-BROKE

Carry on Bud, the floor is yours.  :popcorn:

BTW you could probably get the 2 pdfs in one post by posting one and then the other by way of a "Modify".
Not sure, but it'd be worth a try rather than have to download the 1.5 mb which will a PITA for some.

Quote
The PLL power supply in DS2072A was oscillating.

 :wtf:
 :palm:
Unbelievable

What else is there?  :-BROKE
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 15, 2016, 09:03:46 pm
Mmm...quite shocking this last issue!
if all psu in there "ocillate"  and the "always on"  1khz sig gen too ( why not let it switchable with a pushbutton ? ) it will be a big trouble  :'(
this boy ,and his infinite harmonics, is very close to ch inputs !
what about pwm bcklight then?  |O
Bud, save us...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: senso on March 15, 2016, 09:35:26 pm
Very interesting read.
Good job.
 :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: German_EE on March 15, 2016, 09:36:43 pm
Threads like this are why I find EEVBlog so valuable, there is some damn fine RF detective work going on here.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 16, 2016, 12:48:47 am
Does anyone else think there should be a decoupling cap close to the power pin of the oscillator?
I tried one, it did not make a difference. The proper fix is in Part 3 which I just posted.
Using a tantalum is one option, the other is to put a small resistor (I always use 0.47 Ohm) in series with a 10uf MLCC capacitor to stabilise an LM1117 (or equivalent) LDO.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 16, 2016, 12:55:52 am
Does anyone else think there should be a decoupling cap close to the power pin of the oscillator?
I tried one, it did not make a difference. The proper fix is in Part 3 which I just posted.
Using a tantalum is one option, the other is to put a small resistor (I always use 0.47 Ohm) in series with a 10uf MLCC capacitor to stabilise an LM1117 (or equivalent) LDO.
Third option is to replace the LDO with MLCC tolerant type.
http://www.diodes.com/_files/datasheets/ZLDO1117.pdf (http://www.diodes.com/_files/datasheets/ZLDO1117.pdf)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Monkeh on March 16, 2016, 01:34:13 am
I haven't opened my DS1054Z, but it's easily confirmed from the teardown photos that the exact same LDO configuration is present and oscillating like a cheap motel bed.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: madires on March 16, 2016, 02:01:55 am
Thanks for the thorough investigation!  :-+ It's sad that they have made such stupid mistakes by not reading datasheets. At least we can fix the issues.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on March 16, 2016, 02:08:56 am
Bud,

Thanks again for all the work you've put into this. I also like your brand adjustment photo editing. Nice touch!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: CaptCrash on March 16, 2016, 02:23:22 am
Thanks for presenting this, I really enjoyed your image manipulation.  Well done.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 16, 2016, 02:49:39 am
Quote
Using a tantalum is one option, the other is to put a small resistor (I always use 0.47 Ohm) in series with a 10uf MLCC capacitor to stabilise an LM1117 (or equivalent) LDO.

Quote
Third option is to replace the LDO with MLCC tolerant type.
Yes can do that too but inserting a resistor is an extra work, may need either cut the pcb track or mount it the capacitor in a tombstone manner. Replacing the LDO is extra work too: Yaigol use 1117 adjustable type of regulator, so there is a voltage setting resistor divider with it. Replacing the regulator will require removing the divider or replacing with a new one depending if your new regulator is of a fixed or adjustable type. In both cases i'd think it is not necessary, just do a simple capacitor swap and you will be fine.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 16, 2016, 02:53:55 am
Thanks for presenting this, I really enjoyed your image manipulation.  Well done.

Thank you All for your interest and feedback. Yes wanted to make it a bit funny for easier consumption
 :D
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Monkeh on March 16, 2016, 02:54:16 am
Replacing the LDO is extra work too: Yaigol use 1117 adjustable type of regulator, so there is a voltage setting resistor divider with it. Replacing the regulator will require removing the divider or replacing with a new one depending if your new regulator is of a fixed or adjustable type. In both cases i'd think it is not necessary, just do a simple capacitor swap and you will be fine.

The datasheet he linked is for a drop-in replacement for a 1117. Also, pin 1 (ADJ/GND) is clearly firmly connected to ground in both DS1000Z and DS2000 scopes (it's a fixed 3.3V reg).
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 16, 2016, 03:04:21 am
Ah yes, sorry, i confused it with some other circuit
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 16, 2016, 03:33:00 am
After i posted Part 3 i found my old notes saying i actually measured the Yaigol capacitor with the VNA and it had 6 mOhm of ESR in its dip. A very far cry from the LDO specified limit of 33 mOhm.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on March 16, 2016, 03:56:21 am
Just finished reading Part 3. So, is it fair to say that making the corrections in Part 2 brings a 2000 scope's PLL into a similar condition as the firmware-fixed 1000Z and will lock? In other words, will both models be OK at that point? Then, fixing the LDO oscillation provides additional cleanup applicable to both models, but the values for the 1000Z are TBD.

The final spectrum comparison at the end of Part 3 is awesome.  :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: mimmus78 on March 16, 2016, 04:14:06 am
Thanks buddy ... this post is better than any Netflix series.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 16, 2016, 06:10:06 am
Yaigol use 1117 adjustable type of regulator, so there is a voltage setting resistor divider with it. Replacing the regulator will require removing the divider or replacing with a new one depending if your new regulator is of a fixed or adjustable type. In both cases i'd think it is not necessary, just do a simple capacitor swap and you will be fine.
Actually not, there is NCP1117 3.3V fixed type on your photo. Even if it was adjustable, no resistor change would be needed as vast majority of LDOs have the same reference voltage.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: SaabFAN on March 16, 2016, 06:56:13 am
Well, I guess THAT flushes even the very last moral obstacle against hacking Rigol-Stuff down the toilet.
I certainly don't feel bad about them at all anymore and just added the necessary components to my next Digikey-Order. ^^

Is there a possibility to give the PLL some "proper" values? If I understand it correctly, the Jumpers can be used to disconnect the PLL from the rest of the SPI-Bus.
Should be possible to put a Attiny in there to program the PLL with the right values upon power-up.
Unless the scope is doing some tricky stuff with the PLL under certain operating conditions.

Btw. isn't there a Rigol-Representative here on the Forum? I wonder what he has to say about this apparent aversion to reading the datasheets :)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 16, 2016, 03:51:40 pm
Yes it is possible to control the PLL with your own microcontroller. No the scope did not seem to reprogram the PLL during operation, only programmed the registers at power on.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Mr.B on March 16, 2016, 04:08:36 pm
Bookmark...
Thank you for going to the trouble of doing all this.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 16, 2016, 05:55:55 pm
Thank you and enjoy Part 4.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 16, 2016, 06:40:21 pm
And I am tired to tell you what I think about Yaigol. This time I am going to ask you to tell me what
you think about their level of competency and if their Yingineers read Datasheets.
Maybe they've used one of their own DSO's to confirm their PSU designs and the oscillations/ripple is invisible to it?  ;)

For those watching Bud has offered his Yaigol DSO in the Buy/Sell thread:
https://www.eevblog.com/forum/buysellwanted/fs-rigol-ds2072a-oscilloscope-300mhz/ (https://www.eevblog.com/forum/buysellwanted/fs-rigol-ds2072a-oscilloscope-300mhz/)

Has it had all the fixes to date Bud?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 16, 2016, 07:20:38 pm
Thank you and enjoy Part 4.
All LDOs are oscillating?  Yikes!  :palm:
I'm wondering how they missed that during development. The first time I used an LM1117 I spotted it was oscillating pretty quick and that was only one device. Or have the designers put in the right component and got it replaced by something 'compatible' by the procurement department?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: EV on March 16, 2016, 07:20:57 pm
Thanks Bud! Great work!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: kripton2035 on March 16, 2016, 07:32:02 pm
Thank you and enjoy Part 4.
I enjoyed reading part4 as well as all the previous parts
my thoughts : you deserve to sell your scope at a higher price than a new one !
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Mr.B on March 16, 2016, 07:34:53 pm
@Bud -
Have you approached Rigol about this?
Pointed them at your thread?

You have done a lot of hard work here and they should be grateful.
Perhaps they will take notice and modify for Rev 2...

I have a 2072...
I don't know whether to make your mods or not... (I have the skills and tools to do direct replacements, no way of getting the inductors tuned correctly though.)
I don't know whether to contact Rigol and make a formal complaint...
Hmm... A bit confused as to what I should do.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 16, 2016, 07:41:17 pm
This is really nice work, and interesting. Thanks for taking the time to document it all Bud. However one thing is bothering me.

What effect do these issues have on the actual usage of the scope?

It would be interesting to compare Buds improved scope with an original to see what the differences are in actual use.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 16, 2016, 07:48:33 pm
I was wondering about that too. Clearly there's some design errors in the scope, but it would be interesting to see how they affect the actual displayed waveform on screen under various conditions.

I think it would be useful for anyone with an affected scope to know when - or, indeed, if - they are likely to see artefacts that relate to these issues, and what relevant, quantitative improvement they'd see by opening up the scope and applying the fixes.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Mr.B on March 16, 2016, 07:56:37 pm
+1

Thats why I am at a loss as to whether to do anything about it...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 16, 2016, 08:00:32 pm
In the UK you can return the scope to the supplier under the Consumer Rights Act.

After the first six months the burden is on you to prove that the product was faulty at the time of delivery. In practice, this may require some form of expert report, opinion or evidence of similar problems across the product range. You have six years to take a claim to the small claims court for faulty goods in England, Wales and Northern Ireland and five years in Scotland. This doesn't mean that a product has to last six years - just that you have this length of time in which to make a claim if a retailer refuses to repair or replace a faulty product.

FFI: http://www.which.co.uk/consumer-rights/regulation/consumer-rights-act#link-8 (http://www.which.co.uk/consumer-rights/regulation/consumer-rights-act#link-8)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: kripton2035 on March 16, 2016, 08:16:11 pm
Bud lives in canada ...;)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 16, 2016, 08:22:12 pm
Hi..
Bud says  lt1038  is a fixed reg ...
but from ds i assume it's adjustable!
how can he change it on the fly ?
i dont understand this step :-//
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 16, 2016, 08:23:20 pm
Bud lives in canada ...;)
Many Rigol purchasers live in the UK.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 16, 2016, 08:39:58 pm
+1
Thats why I am at a loss as to whether to do anything about it...
The oscillation in the LDOs is very likely to swing the power supplies out of spec for the devices they power so if you experience random crashes it is a good idea to apply the LDO fixes.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 16, 2016, 08:43:39 pm
+1

Thats why I am at a loss as to whether to do anything about it...
If you don't the uncertainty will nag you till you die.  ;)

+1
Thats why I am at a loss as to whether to do anything about it...
The oscillation in the LDOs is very likely to swing the power supplies out of spec for the devices they power so if you experience random crashes I is a good idea to apply the LDO fixes.
Exactly
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 16, 2016, 08:51:50 pm
I wouldn't personally get my hopes up. A small amount of ripple on a digital supply is unlikely to cause crashes in my experience.

Poor SI on a high speed interface, or buggy code, are far more likely IMHO.

Happy to be proved wrong if someone feels like carrying out a controlled experiment to check.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 16, 2016, 08:55:55 pm
I wouldn't personally get my hopes up. A small amount of ripple on a digital supply is unlikely to cause crashes in my experience.
Expect the oscillation to be in the ballpark of 200 to 300mVpp so it is not a small ripple. On a 3.3V supply it is plain to see with an oscilloscope set to 1V/div.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 16, 2016, 09:07:35 pm
Expect the oscillation to be in the ballpark of 200 to 300mVpp so it is not a small ripple.

I know the theme of the thread is just how tragically incompetent this board's designer clearly was, but seriously...? Even the most inept amateur would spot that amount of ripple, there's no way it wouldn't be noticed.

Again, equally happy to be proved wrong if someone feels like probing an unmodified scope to check. I don't have one.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 16, 2016, 09:22:59 pm
Even the most inept amateur would spot that amount of ripple, there's no way it wouldn't be noticed.
And release it into production?
Heaven forbid, in days gone by they'd be out the door.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: IanJ on March 16, 2016, 10:50:43 pm
Hi all,

Rigol in my opinion will know all about this issue as the scope has been around for a good while, well you would have thought so anyways!.
They will have weighed up everything along the way and risk assessed whether they should have done anything about it.

Great work by BUD though, and you never know as a PR push Rigol might adjust the current BOM in production.

For the rest of us, we can enjoy a home fix courtesy of BUD's great instructions. I'll certainly be looking at it.

Ian.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 16, 2016, 11:02:28 pm
They will have weighed up everything along the way and risk assessed whether they should have done anything about it.

Probably.

One thing that will get their attention is if their distributors find they are having to sort out complaints and court cases from customers.

IANAL, but given Bud's report, I would expect it would be an easy court case to prosecute in the UK's small claims courts.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Nuno_pt on March 16, 2016, 11:07:22 pm
The more difficult part will be the two wire ohm alike, for those that don't have an VNA to measure the OHm range at 1GHz.

The rest till now would be pretty strait forward.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 17, 2016, 12:14:16 am
Right...that coils seems quite tricky to build and put in correctly and are really a critical step. . What's wire exact diameter? 0.25mm ?  And precise orienting?  :o
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 17, 2016, 01:32:12 am
, I would expect it would be an easy court case to prosecute in the UK's small claims courts.

Take it easy guys, it is not worth your time and sweat drugging a spectrum analyser into the courtroom
 ;D
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: c4757p on March 17, 2016, 01:38:44 am
, I would expect it would be an easy court case to prosecute in the UK's small claims courts.

Take it easy guys, it is not worth your time and sweat drugging a spectrum analyser into the courtroom
 ;D

Yes, please. Everything has design flaws, complaining about them is one thing, but we don't need to make the legal system profit unnecessarily over them ::)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: miguelvp on March 17, 2016, 01:42:09 am
Not only that, but Rigol only has to show that their equipment meets the specs published.

So far I haven't seen that not being the case, or did I miss something that shows either the DS1000 or the DS2000 not meeting their claimed specs?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 17, 2016, 01:44:03 am
#30 converts to 0.254mm, some +/- should be ok, i used two different wire thicknesses from the spools i happened to have. Solder them in rabbit ears fashion ( V- shape) and it should work fine. Again, you could search for and buy two 3nH smt inductors, 0603 size and i recall 0805 can also be fitted, since it is required to solder them at right angle a short extension wire is needed to connect one terminal of the right angled inductor to the second solder pad. The pads on the pcb are too small for a repositionedinductor to be soldered directly to them.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 17, 2016, 01:45:48 am
Hi Bud,

Nice work! If you still have the scope, could you please post a picture with the "new" noise floor? I'm curious if it is any better.

PS I can't believe how far they got wrong with LDOs and ESR... I suspect there many more surprises inside. But I got it, you've seen enough and now selling the unit.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 17, 2016, 01:47:06 am
They will have weighed up everything along the way and risk assessed whether they should have done anything about it.

Probably.

One thing that will get their attention is if their distributors find they are having to sort out complaints and court cases from customers.

IANAL, but given Bud's report, I would expect it would be an easy court case to prosecute in the UK's small claims courts.
Prosecute for what? Scopes are working. Good luck to prove that oscillating LDOs makes the scopes being faulty. All you can claim that you are offended by the ripple on power rails  :-DD.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: c4757p on March 17, 2016, 01:58:29 am
PS I can't believe how far they got wrong with LDOs and ESR... I suspect there many more surprises inside. But I got it, you've seen enough and now selling the unit.

That LDO is one made by many manufacturers, and all are subtly different. I bet they used one in prototyping that was perfectly happy in that circuit, then switched to a different (less expensive?) vendor for production. Could be a decision made by the bean counters, few of whom would realize the potential issue there. It still works, so nobody noticed the problem.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 17, 2016, 01:58:57 am
@miguelvp

Questioning of claimed specifications was never in my mind. If i happened to buy a 4 cylinder car with only two cylinders working and the car seller speck-d the car fuel consumption and engine performance based on two cylinders, then the specs are technically correct and it does not make sense to claim otherwise even if i went and fixed the other two cylinders.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 17, 2016, 02:12:55 am
Not only that, but Rigol only has to show that their equipment meets the specs published.

Not in the UK. You only have to show the design was defective, and proportionate damages will then be awarded. Of course, what "proportionate" means will vary from owner to owner and court to court.

It is also and entirely separate issue as to whether it is worth an owner going taking any action whatsoever.

I wonder how many people suffered damage from the Pentium FDIV bug? Nonetheless, Intel took prompt and praiseworthy action in that case, and Intel's reputation was enhanced.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: miguelvp on March 17, 2016, 02:16:57 am
PS I can't believe how far they got wrong with LDOs and ESR... I suspect there many more surprises inside. But I got it, you've seen enough and now selling the unit.

That LDO is one made by many manufacturers, and all are subtly different. I bet they used one in prototyping that was perfectly happy in that circuit, then switched to a different (less expensive?) vendor for production. Could be a decision made by the bean counters, few of whom would realize the potential issue there. It still works, so nobody noticed the problem.

That's a common problem, cost reduction gets designs altered in many products and it only requires someone to sign off on it that might not even be the original designer.

Same thing happened to Jeri Ellsworth on her C64 Direct to TV joystick
https://en.wikipedia.org/wiki/C64_Direct-to-TV

Not sure where I've heard it but pretty much she had to fly to China because the devices were not working, just to find out that cost reduction had altered her whole design, so she had to find a way to make it work while it was in production.

She will be the first one to tell you that the resulting device was a POS, but it was produced with low cost in mind, so it ended up to be what it ended up to be.


Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 17, 2016, 02:21:27 am
, I would expect it would be an easy court case to prosecute in the UK's small claims courts.

Take it easy guys, it is not worth your time and sweat drugging a spectrum analyser into the courtroom
 ;D

Yes, please. Everything has design flaws, complaining about them is one thing, but we don't need to make the legal system profit unnecessarily over them ::)

The legal system wouldn't profit in the UK's small claims court - it is there to get swift cheap justice. No legal representatives are necessary, and plaintifs normally represent themselves. If the defendent wishes to employ lawyers, that is up to them.

It is an excellent mechanism for keeping small claims out of the legal system. Legal costs are not awarded to the loser - which is an excellent incentive against rich defendents trying to intimidate people by spending large amounts of money on lawyers.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: c4757p on March 17, 2016, 02:22:44 am
Minor nitpick, the point is the system doesn't have to be involved in this at all. I don't actually care about the specifics of how your legal system works.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 17, 2016, 02:28:19 am
I don't actually care about the specifics of how your legal system works.
In that case why did you make any comments about it in the first place?!
It is also worth avoiding making incorrect comments on subjects you don't know anything about.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 17, 2016, 02:30:42 am
Have not checked yet if there is an oscillation, but all 1117s in my non- A DS2072 are not NCP1117 from ON semi but from some different manufacturer which I'm unable to recognize.
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=208735;image)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: c4757p on March 17, 2016, 02:37:52 am
I don't actually care about the specifics of how your legal system works.
In that case why did you make any comments about it in the first place?!
It is also worth avoiding making incorrect comments on subjects you don't know anything about.

I made a comment about getting the system involved at all, which has nothing to do with the mechanics about it. The comment about them not needing to make them profit was tongue in cheek anyway, I don't see why it needs to be held to the same standard as if I seriously claimed they would. None of this invalidates my suggestion that we not get them involved at all.

Not making incorrect comments on subjects I don't know anything about is why I didn't explicitly claim they make money on this.

Pays to read completely.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 17, 2016, 02:47:05 am
... And there isn't any LDO oscillation in my scope.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Nuno_pt on March 17, 2016, 02:50:09 am
Have not checked yet if there is an oscillation, but all 1117s in my non- A DS2072 are not NCP1117 from ON semi but from some different manufacturer which I'm unable to recognize.

It could be from Taiwan Semi.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 17, 2016, 02:54:19 am
Have not checked yet if there is an oscillation, but all 1117s in my non- A DS2072 are not NCP1117 from ON semi but from some different manufacturer which I'm unable to recognize.

It could be from Taiwan Semi.
I checked those already, marking does not match with the datasheet.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on March 17, 2016, 03:04:34 am
Questioning of claimed specifications was never in my mind. If i happened to buy a 4 cylinder car with only two cylinders working and the car seller speck-d the car fuel consumption and engine performance based on two cylinders, then the specs are technically correct and it does not make sense to claim otherwise even if i went and fixed the other two cylinders.

That seems rather a false equivalency. If you buy a 4 cylinder car, you expect the specs to be based on all 4 cylinders. In what way are you suggesting that Rigol is juking their specs?

I've been using my DS2000 to make money freelancing for 3.5 years without any measurement errors or faults causing me problems  - and with no service issues except for an encoder that died (and was replaced under warranty). While I'm finding your investigation and tweaking of the hardware fascinating, the issues you've discovered - at least in my unit - have had zero effect on my usage of the DSO.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 17, 2016, 03:08:05 am
Oppsss ..One more  stupid question, forgive me ...
....
which  esr value is better  in these tantalum caps?
Around 0.5 ohms  or even  higher ( 1  or more ..)

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: uChip on March 17, 2016, 03:12:14 am
@Bud
Thank you for your excellent efforts.  I recall you criticizing the PLL when the jitter problem was first discovered.  I think your findings prove without a doubt that your criticisms were all correct.  The PLL fail cannot be blamed on building down to a price point. Since you changed only component values, I doubt you impacted manufacturing cost at all in the PLL circuit and by no more than a few pennies overall.  The tantalums are a bit more expensive but I'll bet that with sufficient effort an equivalent cost solution could be had.  There is no excuse for Rigol not to have gotten this right.  I do agree with what folks said about translation from engineering to production.  I've experienced that myself.  It could explain the wrong ESR caps on the LDOs, but not the wrong values on the PLL.

One thing, most of us do not have the SA to confirm our fixes.  We would be doing it blind and taking it on faith that our scope performance was improved.  Replacing caps is relatively easy, but those hand-fabricated inductors are likely beyond me.  It would be of benefit to many, I think, to swap back to chip inductors of the proper value and retest.

@IanJ
Great opportunity for a "repair" video!  I've really enjoyed to ones you've done before.  If you do it there are several places that you could add value.  One, if you have a 1054Z it would be good to perform the fixes and IDing the component locations on that model.  Two, you could use chip inductors instead of hand fabricated.  Three, if you could perform tests that demonstrated performance improvement using more common tools (DMM, another scope, signal reference), that would allow more of us following along at home to verify our results.

@The folks who question the value of the fixes
I agree with the person who said that ripple is not likely to cause crashes.  By its nature digital logic is fairly robust.  It's far more likely that crashes are caused by flawed software.  Besides, the LDOs Bud fixed were for analog circuits.  The impact of those would be things like offsets just as Bud wrote.  Also things like trigger sensitivity and dare I hope that cleaning up the supplies would improve the noise floor.  I would love to see before and after captures of a 10 MHz 2 mV signal.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Nuno_pt on March 17, 2016, 03:38:55 am
CoilCraft has some inductors 3nH @ 1GHz here http://www.coilcraft.com/apps/finder/rffinder.cfm?mode=post&frequency=500&l=3&core=any&currency=USD&quantity=1000&frequency_unit=khz&L_unit=nH&length_unit=mm&width_unit=mm&width=&length=&utm_source=Inductance+Page&utm_medium=Search+engines&utm_campaign=Inductance+terms&radio_mount=sm&height=&height_unit=mm&acurrent=&acurrent_unit=amp&dcr=&dcr_unit=mohms&showimages=yes (http://www.coilcraft.com/apps/finder/rffinder.cfm?mode=post&frequency=500&l=3&core=any&currency=USD&quantity=1000&frequency_unit=khz&L_unit=nH&length_unit=mm&width_unit=mm&width=&length=&utm_source=Inductance+Page&utm_medium=Search+engines&utm_campaign=Inductance+terms&radio_mount=sm&height=&height_unit=mm&acurrent=&acurrent_unit=amp&dcr=&dcr_unit=mohms&showimages=yes)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on March 17, 2016, 03:44:51 am
... And there isn't any LDO oscillation in my scope.

Interesting. Any chance you have an SA and can check the PLL on your non-A DS2000?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 17, 2016, 03:47:31 am
Good discussion folks, all opinions are welcome. My motivation was to make circuits work as they should, that is all. But having observed what i observed my equipment shopping list will not have  Yaigol again. Life is too short to have too many unknowns.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 17, 2016, 03:47:58 am
... And there isn't any LDO oscillation in my scope.

Interesting. Any chance you have an SA and can check the PLL on your non-A DS2000?
No, I don't have a SA, only a desire to have it  :-DD.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 17, 2016, 03:57:25 am
Good discussion folks, all opinions are welcome. My motivation was to make circuits work as they should, that is all. But having observed what i observed my equipment shopping list will not have  Yaigol again. Life is too short to have too many unknowns.

You've done a nice job of design verification; something which I'm sure we'd all hope and expect the original designer would have done.

Now that you've implemented the fixes, are you able to show any before/after screen captures from the scope itself which show the benefit of these changes?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 17, 2016, 04:09:31 am
I don't actually care about the specifics of how your legal system works.
In that case why did you make any comments about it in the first place?!
It is also worth avoiding making incorrect comments on subjects you don't know anything about.

I made a comment about getting the system involved at all, which has nothing to do with the mechanics about it. The comment about them not needing to make them profit was tongue in cheek anyway, I don't see why it needs to be held to the same standard as if I seriously claimed they would. None of this invalidates my suggestion that we not get them involved at all.

Not making incorrect comments on subjects I don't know anything about is why I didn't explicitly claim they make money on this.

Pays to read completely.

I did read your post completely; it was very short and contained neither those points nor caveats.

Anyway, at this point it has become extremely boring.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 17, 2016, 04:12:30 am
Good discussion folks, all opinions are welcome. My motivation was to make circuits work as they should, that is all. But having observed what i observed my equipment shopping list will not have  Yaigol again. Life is too short to have too many unknowns.

That is a sane conclusion with which I thoroughly agree.

Thank you for your illuminating efforts.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: IanJ on March 17, 2016, 04:43:15 am
Three, if you could perform tests that demonstrated performance improvement using more common tools (DMM, another scope, signal reference), that would allow more of us following along at home to verify our results.

Well, it would have to be........I err, umm, don't own a Spectrum Analyzer (real)......but yes, I was thinking about a video. I have a DS2072 (that thinks it's a DS2202).

Ian.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on March 17, 2016, 04:46:35 am
But having observed what i observed my equipment shopping list will not have  Yaigol again. Life is too short to have too many unknowns.

I can completely understand your feeling, Bud - I've experienced the same sensation myself. But I'm curious if this is the first piece of Chinese test equipment you've purchased?

Having owned briefly / tried extensively an Owon, Hantek, and Siglent beforehand, the Rigol DS2000 was the first cheap Chinese DSO that I could even stand to use (at least in 2012) - and I'd just point out that the PLL/LDO problems you've discovered are in the same league as a plethora of other insane hardware/firmware gaffs I've experienced/seen in a wide range of Chinese brands and Chinese equipment.

As much as many of us (including me) complain about mistakes in Chinese T&ME, in essence, that's what we're paying (or literally, not paying) for: electronic design mistakes, spotty manufacturing, and incomplete and buggy firmware.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on March 17, 2016, 08:38:41 am
Well, it would have to be........I err, umm, don't own a Spectrum Analyzer (real)......but yes, I was thinking about a video. I have a DS2072 (that thinks it's a DS2202).

+1 on the video, Ian. Although the FFT in the scope isn't a (real) SA, might it be good enough? The original noise spectrum and the final clean peak are quite apparent.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 17, 2016, 06:10:22 pm
The internal scope FFT is poor in the first place, I think I did not notice any improvement, its noise is dominated by the 8-bit ADC limits. What should certainly improve is the external FFT for which you capture a long waveform file and load into external software capable of processing the waveform format.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 17, 2016, 06:13:46 pm
Part 7 is now posted, and thermal radiometric files supplied in Part 8.

I am going to take a break as I need to work on other things and writing this article has stolen enough of my sleep time. I may return to Part 5 and 6 later.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 17, 2016, 06:48:34 pm
Oh men, too much work attaching pictures...
Nice job on the Pt. 7 post, see you can do it.  :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 17, 2016, 06:56:07 pm
ah ah bud...this time i discovered this tweak just before you  ;)     the first mod i've done is a little heatsink on the adc... damn hot ! i could'nt put my finger on without burning first!  :'(
now its warm yes , but will not hurt anymore....
Next step, a silent fan !
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Dave Atom on March 17, 2016, 07:00:41 pm
Good discussion folks, all opinions are welcome. My motivation was to make circuits work as they should, that is all. But having observed what i observed my equipment shopping list will not have  Yaigol again. Life is too short to have too many unknowns.

Sorry for what may be a silly question, but I think either I am reading things wrong, or I am just suffering from information overload :

Should I, or should I not, invest in a DS1054Z as my first digital scope ?

I appreciate there are issues, with everything from design, build, hardware, & software, but are they game changers in so much that as a complete novice with little hope (currently) of modifying the scope, should I steer clear of the device ?

(I have noticed the mains lead hasn't been flagged as faulty :] )
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 17, 2016, 07:15:34 pm
Should I, or should I not, invest in a DS1054Z as my first digital scope ?

Yes, repeat no. It is the best device (given some purposes/constraints), repeat there are much more appropriate devices (given other purposes/constraints). You'll never notice the failures, repeat the failures make it useless.

All those statements are correct. Beware those whose statements fall into either camp; you will find both types here.

And I hope you can guess the next thing you should do if you want more specific advice. But please don't do it in this thread - start a new thread!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nidlaX on March 17, 2016, 08:05:57 pm
Very interesting! Another thank you to Bud for conducting this thorough investigation and providing such detailed documentation and instructions. I cannot help but think how much this information would be worth from a product development standpoint (clearly too much for Yaigol to invest in?). I don't own a DS2000 series scope, but I think the information still benefits me as a DS1054z owner (not to mention the entertainment value! :-DD).

Based on the followups from other owners, it seems like part of the issue is yet again attributable to poor quality control? Willy-nilly use of "equivalent" components without checking design compatibility...  :palm: Looks like someone is staking out the Shenzhen market for daily specials again.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: SaabFAN on March 18, 2016, 05:12:56 am
@Dave Atom:
I wouldn't say that the DS1054Z is a bad scope. It just has its flaws that are expected from a company that had to cut corners on everything to get the price down to have even the slightest chance of getting into the market.
So far I haven't run into any serious issues with my scope and really like the 24MegPoint memory, which seems to be one of the things the Rigols really shine at: Every Rigol-Scope comes with tons of memory compared to other brands - even Tektronix and Keysight don't offer that amount of memory in their devices.

What I absolutely don't like is the fact that the Firmware behaves inconsistently. Sometimes I get immediate responses when turning the offset-knob, at other times (same settings btw.) the scope seems to be bogged down by some random stuff and it takes a while for the changes to appear on screen. Also the FFT, as seen in a video by Dave, is horrible.

But it bugs me that I have a potentially horrible looking ADC-Clock in my scope, as well as what appear to be Schroedingers LDO (It could be oscillating, or not... I have to look at it to know)^^
So my Advice: If you can live with the quirks of the Rigols, get one. If not, get an equally expensive Tektronix TDS-Scope on ebay and a healthy supply of electrolytic capacitors :)

Btw. I suspect Siglent, Owon and the other chinese brands to have similar problems. Can somebody check their devices?^^

Has anyone checked the DSA815 for any problems similar to the Rigol-Scopes?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 18, 2016, 05:31:46 am
Oh men, too much work attaching pictures...
Nice job on the Pt. 7 post, see you can do it.  :-+

Thanks for the tip, tautech, it was a bit messy at first but worked in the end.  :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 18, 2016, 06:45:05 am
Oh men, too much work attaching pictures...
Nice job on the Pt. 7 post, see you can do it.  :-+
Thanks for the tip, tautech, it was a bit messy at first but worked in the end.  :-+
Regarding the temperature: It is better to measure using sensors with the case closed so every device has it's 'designed' airflow. Even a little bit of airflow makes a huge difference so it is hard to compare measurements with an open case versus a closed case + airflow.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Howardlong on March 18, 2016, 06:49:10 am

Sorry for what may be a silly question, but I think either I am reading things wrong, or I am just suffering from information overload :

Should I, or should I not, invest in a DS1054Z as my first digital scope ?


This thread probably is not the best one for a prospective $400 scope purchaser to read. While it's not without its features, it took quite some time for the infamous jitter bug to become the stuff of folklore despite many thousands of users.

There is still no other scope out there at this price point with the same specs or real practical use. If $400 is your price point, it's end of story.

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 18, 2016, 06:57:46 am
There is still no other scope out there at this price point with the same specs or real practical use. If $400 is your price point, it's end of story.
There are and with better specs, GDS-1000B series GWinstek. The only advantage of 1000Z is ability to unlock.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Howardlong on March 18, 2016, 07:04:08 am
There is still no other scope out there at this price point with the same specs or real practical use. If $400 is your price point, it's end of story.
There are and with better specs, GDS-1000B series GWinstek. The only advantage of 1000Z is ability to unlock.

I'd like to see a 1:1 to back that up in terms of specs and practical use.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Alex Eisenhut on March 18, 2016, 11:33:40 am
Super awesome. Is it worth it to create a Digikey BOM or outright sell a kit with all parts required for a fix?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 18, 2016, 01:31:19 pm
Hi..
Bud says  lt1038  is a fixed reg ...
but from ds i assume it's adjustable!
how can he change it on the fly ?
i dont understand this step :-//

Sorry my bad, this is what happens when you write in the middle of the night and after 9 months...

I replaced with LT3080, an adjustable regulator with only one set resistor. So I removed one resistor and replaced the other - see the datasheet for the set resistor formula.
http://cds.linear.com/docs/en/datasheet/3080fc.pdf (http://cds.linear.com/docs/en/datasheet/3080fc.pdf)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 18, 2016, 02:34:36 pm
Some additional supporting artefacts for the project articles:

Just for fun I attached demodulated audio for the DS2072A PLL before and after the fix. The bad PLL had FM modulation that could be demodulated into audible range. I did it with my HP 8594E spectrum analyzer that had that capability. In the Before mp3 file nasty modulation is present, this is how your unfixed PLL would sound if you tune to it at 1GHz with a FM receiver. In the After mp3 file there is no modulation, only background noise which I artificially made louder because the audio was too quiet.

A zip archive with a video of the 6.3V shared power supply rail oscillating. Had to zip it because could not attach a video file.

A high res (well sort of) version of the landscape photo of the board from Part 4 with the oscillating regulators locations marked.

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 18, 2016, 02:42:28 pm
ah ah bud...this time i discovered this tweak just before you  ;)     the first mod i've done is a little heatsink on the adc... damn hot ! i could'nt put my finger on without burning first!  :'(
now its warm yes , but will not hurt anymore....
Next step, a silent fan !

Interesting, Emi. I mounted mine with the fins in vertical orientation. I believe I used Digikey p/n 294-1150-ND

(http://media.digikey.com/photos/CTS%20Photos/APF19-19-13CB%5EA01.JPG)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 18, 2016, 03:08:41 pm
Now that you've implemented the fixes, are you able to show any before/after screen captures from the scope itself which show the benefit of these changes?

I did not make before screen captures. The original goal was to fix the dysfunctional PLL and then it dragged into fixing its power regulator and then the other regulators. All that time the scope was face down on the bench and all I could only reach was the power button. Second - which some of people still do not seem to understand - this was about bad design practices per se and not about chasing improvements. Some people are OK to live in a house with the roof flapping in the breeze as long as the roof is not leaking. I would go and fix the roof. Third, if someone wants to do a compare he will have to design proper test cases first. One cant estimate improvements by just looking at the screen noise trace, all he will see will be noise generated in LMH6518 voltage control amplifier in the scope analog front-end which is so high that it even masks 8-bit ADC noise. And by the way, don't waste your time trying to measure the noise trace by enabling measurements/statistics - I found readings will depend on the position of the trace on the screen, which is another stupid "feature".


 
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 18, 2016, 05:10:10 pm
Oh men, too much work attaching pictures...
Nice job on the Pt. 7 post, see you can do it.  :-+

Thanks for the tip, tautech, it was a bit messy at first but worked in the end.  :-+
Yep, pic compression is the key to getting lots of content into ones posts, glad you've got that sorted.

That you've got quality pics it the pdf's is great too for those wanting to have a good look.  ;)


Would you consider reworking the previous parts by way of "Modify" and put the pdf content into the body of each post?
Yeah, I know it's a bit of work, but man that'd really top off your great work and this thread.  8)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: pa3bca on March 18, 2016, 08:15:11 pm
A high res (well sort of) version of the landscape photo of the board from Part 4 with the oscillating regulators locations marked.
Had to look twice, almost missed it  :)
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=209101)
I am definitely going to open my 2072A en probe the PLL with an SA. (The SA is a Rigol 815, so I hope they are not in cahoots with each other...)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: pa3bca on March 18, 2016, 10:59:53 pm
Well my January 2014 DS2072A looks not as bad as Bud's specimen.
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=209143)
Also I checked all the regulators and none of them oscillate. (checked with a 1074Z and the SA).
So what gives?  :-// :-//

The PLL however is not totally clean (not as it should be). But my measuring method is rather unprofessional as can be seen in the photo (I wanted a quick and dirty first impression). But I suspect that if I attach a balun to the diff output the spectrum should not get worse?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 18, 2016, 11:02:37 pm
Well my January 2014 DS2072A looks not as bad as Bud's specimen.

Could you please compare your part numbers (of LDO-s) with those on Bud's scope?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: pa3bca on March 18, 2016, 11:15:03 pm
#2 on Bud's photo
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on March 19, 2016, 01:46:01 am
Hi. I'm "dicking" with coil loops  :)
Is this  tool  good enough  for  a  serious Job?
I would obtain the correct 3nH even  with thicker wire. .
http://www.eeweb.com/toolbox/loop-inductance/ (http://www.eeweb.com/toolbox/loop-inductance/)
Im really unable to handle such microbic #30  :palm:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 19, 2016, 01:40:13 pm
Thanks folks for testing. Your PLLs are wobbly. Would you guys want to go ahead and make the PLL change and retest ?

How did you check for oscillation? You may need a spectrum analyzer on the rail.

Check the 6.3V rail for oscillation, it was strongest spot in my case, refer to the attached picture with the blue arrow pointing to the test location (rightmost terminal of the LDO)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 19, 2016, 01:53:57 pm
Is this  tool  good enough  for  a  serious Job?

I think it is, I tried with #30 thickness that I used, it produced same result.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 19, 2016, 02:11:03 pm
Well my January 2014 DS2072A looks not as bad as Bud's specimen.
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=209143)
Also I checked all the regulators and none of them oscillate. (checked with a 1074Z and the SA).
So what gives?  :-// :-//


That gives exactly this:

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=209522;image)

That Yaigol scope owners are at the mercy of which part suppler Yaigol used for their batch of oscilloscopes, the phase of the moon, or how much the Earth shakes when their neighbor's dog farts. Isn't this is what Quality Control is supposed to take care of.

For the LDO try locating the manufacturers datasheet and see if it spells requirements on output cap ESR. As to the PLL I think I showed sufficient evidence the design is incorrect.

[/quote]
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 19, 2016, 02:26:07 pm
Would you consider reworking the previous parts by way of "Modify" and put the pdf content into the body of each post?

Will do when get some free time ...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 19, 2016, 11:55:59 pm
...Isn't this is what Quality Control is supposed to take care of.

Edit: Sorry I read something into your post that wasn't there - posting too late at night after a drinks is not a good idea.  :-[

No, it is not.

A well known saying in manufacturing used to be 'you can't test in quality'. Meaning depending on QC as the last line of defence will always fail eventually.
The only path to quality is to make it correctly. That is where the failure is, not QC.





Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 20, 2016, 12:05:38 am
I have prepared the oscilloscope MSO2072A again for a measurement.
With the E-field probe, I can see no oscillate. The peaks at 500 kHz are visible along the whole motherboard.
You are measuring the wrong pin! The middle pin/ tab is the output of the 1117 regulators. If they oscillate it is clear to see with a normal probe and usually at a frequency you could hear.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on March 20, 2016, 01:27:35 am
Here the middle pin. Does not look like oscillate. Or do I measure wrong?
You have different LDO ICs, the same as in my oscilloscope which don't oscillate either.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 20, 2016, 05:31:14 am
I have prepared the oscilloscope MSO2072A again for a measurement.
With the E-field probe, I can see no oscillate. The peaks at 500 kHz are visible along the whole motherboard.
You are measuring the wrong pin! The middle pin/ tab is the output of the 1117 regulators. If they oscillate it is clear to see with a normal probe and usually at a frequency you could hear.
Here the middle pin. Does not look like oscillate. Or do I measure wrong?
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?
action=dlattach;attach=209672)
This looks clean enough to me! All in all it starts to point towards a certain batch of oscilloscopes which might be affected.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Alex Eisenhut on March 20, 2016, 07:42:49 am
Given the tremendous PCB real estate, Rigol could have saved 5 cents by using a printed inductor instead of a discrete inductor, seems to me. 3nH works out to about a 500 mils +- 50% on realistic stackups.

Am I naive?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: krivx on March 20, 2016, 09:50:21 am
Given the tremendous PCB real estate, Rigol could have saved 5 cents by using a printed inductor instead of a discrete inductor, seems to me. 3nH works out to about a 500 mils +- 50% on realistic stackups.

Am I naive?

Possibly a printed inductor was considered to be too "baked in", there isn't much scope to change values later on.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Alex Eisenhut on March 20, 2016, 10:29:57 am
Given the tremendous PCB real estate, Rigol could have saved 5 cents by using a printed inductor instead of a discrete inductor, seems to me. 3nH works out to about a 500 mils +- 50% on realistic stackups.

Am I naive?

Possibly a printed inductor was considered to be too "baked in", there isn't much scope to change values later on.

Understood, but the PLL is not changing like the LDOs can, right? What's the second source for a ADF4360-7?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: krivx on March 21, 2016, 10:19:40 pm
Given the tremendous PCB real estate, Rigol could have saved 5 cents by using a printed inductor instead of a discrete inductor, seems to me. 3nH works out to about a 500 mils +- 50% on realistic stackups.

Am I naive?

Possibly a printed inductor was considered to be too "baked in", there isn't much scope to change values later on.

Understood, but the PLL is not changing like the LDOs can, right? What's the second source for a ADF4360-7?

To be honest, I'm not familiar with the part. Do Analog make a range that use the same footprint? Moving to a cheaper or more available part in the same series is my first thought.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 22, 2016, 06:10:46 pm
I started populating Part 5 (https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg890966/#msg890966), pls go to the first page of the thread to read.
It is again 3am in the morning... oh boy.

EDIT March 24:  Added JFET buffer info.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 22, 2016, 08:45:11 pm
Part 5. Front End performance
This may be kind of stupid, why attenuate and then compensate by amplifying. My guess it is a compromise to have an input stage with wide range of V/Div settings.

I've just emerged from a Tek 465's front end. For comparison that consists of
The 0dB+0dB+full gain -> 5mV/div, of course.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 22, 2016, 09:17:57 pm
So how come the total loss of the two attenuators is 48dB but we measured only 32dB at VGA output? Apparently the VGA compensates for the missing 16dB loss. This may be kind of stupid, why attenuate and then compensate by amplifying. My guess it is a compromise to have an input stage with wide range of V/Div settings.
This is actuallly very common in oscilloscope front-ends. The atttenuator also serves as an overvoltage protection circuit.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 26, 2016, 10:35:32 am
Part 5 now complete.

https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg890966/#msg890966 (https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg890966/#msg890966)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 29, 2016, 03:01:05 pm
How did I make these screenshots ?
 ::)

Bandwidth test
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=212840;image)

Raise/Fall time test
(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=212842;image)



Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 29, 2016, 04:58:06 pm
How did I make these screenshots ?

Two practical options come to mind:
Mirrored the R in some editing software, or changed the image in the firmware, recalculated the checksum and installed it.

The 2nd way is cooler, so I hope thats what you did :)

3rd option is mounting the installed filesystem, find the image and change it. That would get bonus points as I think no-one else has done that before...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 29, 2016, 05:07:23 pm
Sorry I meant how did I manage to measure a 800MHz signal and get such good rise time on a 70/300MHz scope.
(the screenshots have some clues   :P )
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 29, 2016, 05:23:48 pm
Doh - you even put red ellipses there.

I'm going back on holiday...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 29, 2016, 05:32:47 pm
So did ya hack the VGA into 900MHz mode?

Perhaps by resetting it after the scope had already started so it went into full bandwidth mode?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 29, 2016, 06:08:20 pm
You're f***ing with our heads Bud, please put us out of our misery.  :-//
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: T3sl4co1l on March 29, 2016, 07:26:54 pm
I'm going to say direct injection into ADC input.

Tim
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: krivx on March 29, 2016, 07:58:51 pm
I'm going to say direct injection into ADC input.

Tim

This seems likely, should it be surprising that the firmware will happily go along with this and give measurements well outside the specs? I'm not sure what the best method for handling this would be. 
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 29, 2016, 08:29:48 pm
This seems likely, should it be surprising that the firmware will happily go along with this and give measurements well outside the specs? I'm not sure what the best method for handling this would be.

I would leave it as is because I don't see clear benefits in "sanity check" in this case because that would decrease "hackability". This also complicates the code, needless to say firmwares are not perfect, more complications potentially would make it less stable/feature rich.

Anyway, I think most measurements functions work with curves, not with measurement points. Performing sanity checks on this is just to tricky and quite pointless, imho.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Circlotron on March 29, 2016, 08:37:32 pm
Sooo..... who's going to be the first to offer a drive-in-drive-out scope update service for this baby?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on March 29, 2016, 08:40:17 pm
Sooo..... who's going to be the first to offer a drive-in-drive-out scope update service for this baby?
The parts won't cost much, but the labour........
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 29, 2016, 08:42:20 pm
This seems likely, should it be surprising that the firmware will happily go along with this and give measurements well outside the specs? I'm not sure what the best method for handling this would be.

I would leave it as is because I don't see clear benefits in "sanity check" in this case because that would decrease "hackability".

Please explain the causal connection - if there is one.

Quote
This also complicates the code, needless to say firmwares are not perfect, more complications potentially would make it less stable/feature rich.

I can make it infinitely "feature rich", provided it isn't required that the features actually work.

Quote
Anyway, I think most measurements functions work with curves, not with measurement points.

I really don't understand what you are trying to say. A digitising scope can only measure points. Waveforms are only curves, until you are dealing at the level of individual photons and electrons and quantum, physics.

Quote
Performing sanity checks on this is just to tricky and quite pointless, imho.

If the manufacturers carelessly get that wrong, what else have they carelessly got wrong?

Old saying: "Fool me once, shame on you. Fool me twice, shame on me".
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 29, 2016, 08:56:27 pm
I really don't understand what you are trying to say. A digitising scope can only measure points. Waveforms are only curves, until you are dealing at the level of individual photons and electrons and quantum, physics.

You move cursors on a waveform, not between points. Analytic functions (or whatever they called) work on waveforms. Why should they care how and what waveform was acquired? In some cases it can be an indication that something is wrong or outside the speck. But this is not a proper self-test for this.

If the manufacturers carelessly get that wrong, what else have they carelessly got wrong?

Why do you think this is wrong? Sorry, I feel like you just falling into "this is wrong and everyone who does not share my point of view is incompetent" without any reasoning.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 29, 2016, 09:26:53 pm
I really don't understand what you are trying to say. A digitising scope can only measure points. Waveforms are only curves, until you are dealing at the level of individual photons and electrons and quantum, physics.
You move cursors on a waveform, not between points. Analytic functions (or whatever they called) work on waveforms. Why should they care how and what waveform was acquired? In some cases it can be an indication that something is wrong or outside the speck. But this is not a proper self-test for this.

Ah. You mean functions that work on continuous curve inferred by interpolating between the sampled points. So that is going to depend on the interpolation chosen, the circumstances undet which the interpolation is and isn't valid, and on whether the implementation is correct.

Is there a hint there?

Quote
If the manufacturers carelessly get that wrong, what else have they carelessly got wrong?
Why do you think this is wrong? Sorry, I feel like you just falling into "this is wrong and everyone who does not share my point of view is incompetent" without any reasoning.

Please don't snip the relevant bits in order to (try to) make a point. You wrote "Performing sanity checks on this is just to tricky and quite pointless".

If an instrument doesn't pass a sanity check, should you continue to put faith in the instrument?

Old saying: "Fool me once, shame on you. Fool me twice, shame on me".
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 29, 2016, 09:31:42 pm
Sorry I meant how did I manage to measure a 800MHz signal and get such good rise time on a 70/300MHz scope.
(the screenshots have some clues   :P )

Display mode in the top screen is X-Y. You're feeding in an external, slower time base on the X channel.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 29, 2016, 09:50:22 pm
Okay, I think I was too strong on statements. I don't say "no check is ever needed". I say four things 1) I don't trust rigol implementing them 2) shouldn't be part of analytical functions. 3) may affect hackability 4) sanity check is very limited when analyzing unknown waveform. And here is why I think so.

1)
analytical functions != Input validation is a different thing. Checking the input range or "space between points" is fine. But...

2)
If it is too strict on checking inputs this may greatly harm hackability. How so? Imagine you removed restriction on bandwidth. But the scope "doesn't know" about this. So it can indicate a failure in this case. Or if I "overclock" it it may refuse work faster because "it checks the specs".

3)
It happened to me I'm a software developer, so I know a little bit about software. I didn't get your point about features, but I repeat my statement: more code -- more hassle to maintain it. If I knew they have good software specialists I would welcome more checks. But since it's rigol I have a fear that they don't have expertise. They can easily degrade scope performance when adding more validation. And it's not uncommon to see "software gone mad".

4) I think best check is the analysis of a signal with a known waveform. I'm not sure it is possible to catch most failures just by analyzing user input.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Gixy on March 29, 2016, 10:29:41 pm
@AndyC:
This is the Cursor menu, X-Y is relative to the display of cursors, not the acquisition mode.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Gixy on March 29, 2016, 10:46:32 pm
Bandwidth means -3dB at max frequency. Let's suppose your input signal amplitude is 5V, you have here 4mV, so an attenuation of more than -61dB, so clearly outside bandwidth. The sampling rate being 2Gs/s, you're still in the Nyquist ratio of 2 samples/period, so the digitalized signal is still valid.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 29, 2016, 11:40:48 pm
How did I make these screenshots ?

Is there any way that you can force the scope to show just the ADC samples, without interpolation / reconstruction / post-capture filtering?

For the rise/falltime, which points are being measured? What happens when the front-end is overloaded? Is it simply measuring noise and finding a signal?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 30, 2016, 01:16:31 am
Thanks guys for participating in the discussion. I will answer in the evening when get home, i do not like typing on my mobile. For now just can say there was no fiddling with the clock frequency, these are actual shots of high frequency and low rise/fall time signals. And still there is a common clue in both screenshots that seems has not been spotted yet.  :)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 30, 2016, 01:28:14 am
And still there is a common clue in both screenshots that seems has not been spotted yet.  :)

My guess is you hacked the input attenuator -- removed/modified low-pass filter.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 30, 2016, 01:33:32 am
The sampling rate being 2Gs/s, you're still in the Nyquist ratio of 2 samples/period, so the digitalized signal is still valid.

I agree wit this. Removing interpolation and leaving only datapoints should show something triangle-like. Plus some input hacking imho.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: AndyC_772 on March 30, 2016, 01:39:36 am
@AndyC:
This is the Cursor menu, X-Y is relative to the display of cursors, not the acquisition mode.

Ah, OK, fair enough.

Perhaps it's something to do with the signal level being extremely low (I see measurements of just a few mV... not sure how exactly they're being calculated)...? Very small amplitude means the system isn't limited by slew rate, because the V/sec rate is still within limits even if the input frequency is high.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tggzzz on March 30, 2016, 03:07:11 am
The sampling rate being 2Gs/s, you're still in the Nyquist ratio of 2 samples/period, so the digitalized signal is still valid.

I agree wit this. Removing interpolation and leaving only datapoints should show something triangle-like. Plus some input hacking imho.

Why are you choosing that specific reconstruction? Why not  a zero-order hold or, better, just the impulses?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 30, 2016, 08:41:21 am
Why are you choosing that specific reconstruction? Why not  a zero-order hold or, better, just the impulses?

I think I meant "just impulses" (=no reconstruction?). I'm no expert in this stuff, it's just a picture that popped into my head -- dots connected with straight lines. May be because I saw this on youtube when the guy chose "no interpolation" on the scope. Probably, it was in "the signal path blog" and with a review of a 100GHz scope.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 30, 2016, 09:21:48 am
Thanks guys for participating in the discussion. I will answer in the evening when get home, i do not like typing on my mobile. For now just can say there was no fiddling with the clock frequency, these are actual shots of high frequency and low rise/fall time signals. And still there is a common clue in both screenshots that seems has not been spotted yet.  :)

The first screenshot has the bandwidth limit on - but is still measuring 800MHz...
Both traces look very sharp compared to the equivalent signal on my DS4k - is averaging turned on or is that typical when the scope is stopped?



Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 30, 2016, 01:23:09 pm
Bandwidth means -3dB at max frequency. Let's suppose your input signal amplitude is 5V, you have here 4mV, so an attenuation of more than -61dB, so clearly outside bandwidth. The sampling rate being 2Gs/s, you're still in the Nyquist ratio of 2 samples/period, so the digitalized signal is still valid.

Nope, the waveform quickly becomes fuzzy after you cross the VGA set bandwidth limit.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 30, 2016, 02:21:00 pm
Tim got it right or almost right, and a few other people were close. It could be seen that the mv/Div was set very low, 500uV/ in one shot and 5mV/ in the other, but there was no trace noise in the shots, look how noise-free the waveform is.

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=213073;image)

In Part 5 I said the variable bandwidth VGA in the front-end is responsible for generating most of the noise in the path. Noise-free waveforms in the screenshots with such small mv/Div could only be obtained if to bypass most of the input stage and inject the signal into the ADC buffer. It was too much problem to get the signal right into the ADC pins, it was easier to do it with the ADC buffer stage as shown in the following picture.

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=213075;image)

I unsoldered the two SMT resistors (they are two zero Ohm jumpers) located near the VGA and that gave me access to the LMH6552 ADC buffer input. hooked up a RF balun to it to convert differential input into single ended input, with a pigtail microcoax soldered to the other end of the balun.

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=213083;image)

I could then perform sweeps and do bandwidth measurements of the ADC buffer + ADC, lets take a look again what I posted in Part 5:

(https://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/?action=dlattach;attach=213079;image)

We are looking at the blue line which is the ADC buffer + ADC transfer function. In fact it had gain so the chart was normalized to the maximum gain point which occurred at around 300MHz with 5dB gain. Therefore if we consider the leftmost end of the blue line to be 0dB, the -3dB point to the right of it and relative to it would be around 800...850MHz (the blue line). So technically this part of the signal path is capable of 800MHz bandwidth, and that was what you saw in the screenshots with a sinewave and raise time test.

I recall doing a few sweeps and if I remember correctly the scope triggered up to 600MHz. Above that it rolled but I could stop it and see the waveform up to 800MHz (with 2GS/ sample rate, single channel mode). So basically the capability is there but is crippled by the VGA bandwidth limit. Technically the VGA SPI bus could be hacked, commands intercepted and corrected so in Full bandwidth mode it could be set to say 600MHz, so what you get is  a 500MHz scope for almost no extra money. The problem however is with highjacking the VGA SPI bus tracks, doing this would require unsoldering the LMH6518 VGA and perhaps fitting it on a small PCB and retrofit that PCB back to where the VGA was. Too much trouble, though in theory can be done. May be I would have done it, had I not decided by the time I will not keep the scope. Also, I had not thoroughly tested the scope in all modes with this, beside the FFT which still worked correctly. I think the frequency counter became shaky and gave incorrect readings above 450MHz or so. Anyway, this may be an interesting info for a determined person to explore more.

So, [Dave mode] if you liked this info, give it a thumbs up, that always helps [/Dave mode]  :D

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 30, 2016, 03:48:19 pm
Actually a quick and dirty method would be to use the above schematic trick with a 1:4 balun and feed its input coax to may be the back panel or to one channel's BNC on the front panel of the scope, The input stage of one channel can be sacrificed for that if there is a desperate need in a higher bandwidth. Scope V/Div settings would not work in this case for that channel and the input must be kept less than 100mV RMS to not overload the ADC buffer.

A variation of it could be reusing the attenuator stage and may be reusing everything else and skipping the VGA. That would give possibility to change V/Div and perhaps vertical position adjustment. Still, V/Div would not be accurate because some of gain adjustment occurs in the VGA via the SPI bus control.   :blah:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 30, 2016, 05:08:11 pm
What do you think would happen if the VGA was able to be reset - i.e. remove power and then restore it.

If I read it correctly its power on state according to the datasheet is Full bandwidth, low gain and no attenuation.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on March 30, 2016, 07:52:31 pm
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 30, 2016, 07:58:47 pm
So basically the capability is there but is crippled by the VGA bandwidth limit.

That's why I always want source codes at hand :(. It would be just a few lines code changed to "unlock" the performance. It's not just about scopes, in general a lot of hardware is capped by software.

So, [Dave mode] if you liked this info, give it a thumbs up, that always helps [/Dave mode]  :D

Thumbs up! :D
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: T3sl4co1l on March 30, 2016, 10:19:48 pm
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!

Aliasing is desirable for an oscilloscope.

With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

Tim
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rch on March 30, 2016, 10:31:52 pm
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!

Aliasing is desirable for an oscilloscope.

With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

Tim


I remember when that was the only way to make a 1GHz 'scope!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Alex Eisenhut on March 30, 2016, 10:48:18 pm
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!

Aliasing is desirable for an oscilloscope.

With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

Tim

Tektronix 547 + 1S1 plugin.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: exe on March 30, 2016, 11:26:35 pm
Tektronix 547 + 1S1 plugin.

Is there any plugin for storing and navigating waveforms?  ;D
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 31, 2016, 12:40:10 am
With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

DS2072a price is $839 or something.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on March 31, 2016, 12:52:02 am
What do you think would happen if the VGA was able to be reset - i.e. remove power and then restore it.

If I read it correctly its power on state according to the datasheet is Full bandwidth, low gain and no attenuation.

But cycling the power may also reset the DC offset calibration (im still not sure if some or all of it done by the VGA)

I am now thinking that in fact you only need to highjack the Chip Select line, the Data abd Clock perhaps could be simply paralleled with the scope bus. In which case should be possible to leave the VGA on the board.


Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: ghulands on March 31, 2016, 05:53:37 am
I'm looking to get a DS4024 and was curious if anyone who has one has checked to see if it too has this as well.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: el_dooderino on March 31, 2016, 06:23:43 am
Thanks for doing this! Really enlightening. Besides the obvious improvement of the clock spectrum, do you notice a difference on captured waveforms? Perhaps a lower noise floor or less jitter on captured signals?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on March 31, 2016, 06:28:16 am
I'm looking to get a DS4024 and was curious if anyone who has one has checked to see if it too has this as well.

Connor Wolf did a teardown of one here:
https://www.youtube.com/watch?v=_J1pVlqMIHM (https://www.youtube.com/watch?v=_J1pVlqMIHM)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: ghulands on April 02, 2016, 03:21:31 am
I'm looking to get a DS4024 and was curious if anyone who has one has checked to see if it too has this as well.

Connor Wolf did a teardown of one here:
https://www.youtube.com/watch?v=_J1pVlqMIHM (https://www.youtube.com/watch?v=_J1pVlqMIHM)

Thanks for the link. I couldn't see the PLL circuit in that video, but I think I did find it in another one of his videos

https://youtu.be/MbWz8yB_vTQ?t=701 (https://youtu.be/MbWz8yB_vTQ?t=701)

It's not the sharpest image that i grabbed from the video. But i think this might be it. Can anyone confirm?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on April 02, 2016, 06:21:21 am
Thanks for doing this! Really enlightening. Besides the obvious improvement of the clock spectrum, do you notice a difference on captured waveforms? Perhaps a lower noise floor or less jitter on captured signals?

This.

Does the 'fix' make the slightest difference to the performance of the 'scope?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: EEVblog on May 14, 2016, 06:36:22 pm
Can't believe I haven't seen this thread!
The forum is just too big I guess...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: krivx on May 14, 2016, 07:15:19 pm
Can't believe I haven't seen this thread!
The forum is just too big I guess...

It seems like pretty good video material...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: kcbrown on May 18, 2016, 03:08:44 am
Quite some time back, in a different thread, I wrote:

In regards to your hardware issue guess, it well may be the case. I have opened my 2072a to fix the ADC clock problem and what I found beside that problem was bunch of other hardware related problems all over the board, along and across. In one instance reviewing a circuit that occupied 1 square inch of space on the  PCB I counted 10 design errors! Wrong component selection, wrong design, wrong circuit layout. 10 errors per sq inch,

Have you detailed these errors somewhere, and especially the corrections you'd make to fix the errors you found?   If so, where did you write them up?

If not, why not?   Such an analysis could be immensely useful, or at the very least highly instructive.


Boy, did Bud deliver!!   This is awesome stuff.   MAJOR thumbs up!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on May 18, 2016, 02:32:53 pm
Someone posted in a other thread 2000 line is/will be soon discontinued. Good to see that crap go. Until then feel free to spread the word and repost so more people get educated on the meaning of "best bung for the buck".
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on May 18, 2016, 02:46:43 pm
Someone posted in a other thread 2000 line is/will be soon discontinued. Good to see that crap go. Until then feel free to spread the word and repost so more people get educated on the meaning of "best bung for the buck".
:scared:
That's not a typo is it?
 :popcorn:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Circlotron on May 19, 2016, 03:37:05 pm
"best bung for the buck".
Or more realistically "least worst scope for your money".
I've got one. When I don't know what is happening on the inside, most everything looks good on the outside. That's not to excuse sloppy hardware and firmware for a moment, and I wish they were both perfect, but the way I use my scope 99% of the time there are no obvious shortcomings. Having said that, I'm all for uncovering what ought to be improved.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on May 19, 2016, 04:06:07 pm
It's also worthy to note that Rigol did make improvements/corrections to this and other models and devices since their introduction.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: kripton2035 on May 19, 2016, 04:13:20 pm
the only solution : win a keysight next year !
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on May 19, 2016, 04:41:34 pm
Yes! I shall enter again. Next time for sure. LOL!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: kripton2035 on May 19, 2016, 07:42:11 pm
and as you are american, if you win the taxes only of the keysight makes the price of the rigol ... LOL...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on May 20, 2016, 03:26:32 am
Yeah, spend a Rigol, get a Keysight. Sounds like a good deal to me. :-+
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on May 23, 2016, 02:29:35 am
Looks like Keysight engineers understand PLL design much better than Rigol engineers!  :popcorn:

https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/ (https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/)

https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/ (https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 05:06:04 pm
Looks like Keysight engineers understand PLL design much better than Rigol engineers!  :popcorn:

https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/ (https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/)

https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/ (https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/)
Of course they do. They detect if there is no PLL lock. Rigol just silently outputs the variable frequency jittery crap into the ADC clock.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 05:20:19 pm
Looks like Keysight engineers understand PLL design much better than Rigol engineers!  :popcorn:

https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/ (https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/)

https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/ (https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/)
Of course they do. They detect if there is no PLL lock. Rigol just silently outputs the variable frequency jittery crap into the ADC clock.

But it seems to still meet its specs? Are you saying it was over-engineered? :popcorn:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 05:30:41 pm
Looks like Keysight engineers understand PLL design much better than Rigol engineers!  :popcorn:

https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/ (https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/)

https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/ (https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/)
Of course they do. They detect if there is no PLL lock. Rigol just silently outputs the variable frequency jittery crap into the ADC clock.

But it seems to still meet its specs? Are you saying it was over-engineered? :popcorn:
Who meet the specs, Rigol? Certainly was not the case For DS1054Z because it had apparent effects on the waveform captured. Until they firmware(ish) kinda "almost" fixed non locking PLL, almost because the clock still remained not that clean, and it's not certain if 100% of the scopes became good enough to not have visible issues. This varies from scope to scope and you don't know how bad your particular unit is.
As of Keysight, scope checks and informs you if PLL gone wrong, therefore you know when the scope cannot be trusted.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 05:51:31 pm
Looks like Keysight engineers understand PLL design much better than Rigol engineers!  :popcorn:

https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/ (https://www.eevblog.com/forum/testgear/agilent-dsox2024-won't-boot/)

https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/ (https://www.eevblog.com/forum/testgear/oh-no!-i'm-never-buying-any-agilent-keysight-equiment-ever-again!/)
Of course they do. They detect if there is no PLL lock. Rigol just silently outputs the variable frequency jittery crap into the ADC clock.

But it seems to still meet its specs? Are you saying it was over-engineered? :popcorn:
Who meet the specs, Rigol? Certainly was not the case For DS1054Z because it had apparent effects on the waveform captured. Until they firmware(ish) kinda "almost" fixed non locking PLL, almost because the clock still remained not that clean, and it's not certain if 100% of the scopes became good enough to not have visible issues. This varies from scope to scope and you don't know how bad your particular unit is.
As of Keysight, scope checks and informs you if PLL gone wrong, therefore you know when the scope cannot be trusted.

It was discussed on page 4 of this thread - about DS2k not the earlier issue about DS1k. AFAIK no-one found any problem with the DS2k in operation. Doesn't that deserve some more scrutiny? How come it doesn't matter? Is it being hidden by the poor FFT?

I think the DS1k problem was only visible once the data was extracted from the scope and an FFT run outside the scope? Perhaps that is also the case here.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 05:59:10 pm
I think the DS1k problem was only visible once the data was extracted from the scope and an FFT run outside the scope? Perhaps that is also the case here.
No, it was perfectly visible on the scope screen. Dave even made a video about this.
https://www.youtube.com/watch?v=K1IJH9aJvgE (https://www.youtube.com/watch?v=K1IJH9aJvgE)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 06:07:58 pm
I think the DS1k problem was only visible once the data was extracted from the scope and an FFT run outside the scope? Perhaps that is also the case here.
No, it was perfectly visible on the scope screen. Dave even made a video about this.
https://www.youtube.com/watch?v=K1IJH9aJvgE (https://www.youtube.com/watch?v=K1IJH9aJvgE)

Ah yeah, but that was fixed by a firmware update - I was talking about what was left after the firmware update. I'm trying to find it now...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on May 25, 2016, 06:08:28 pm
It was discussed on page 4 of this thread - about DS2k not the earlier issue about DS1k.
You must have missed following this link in the OP:
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777 (https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 06:15:17 pm
It was discussed on page 4 of this thread - about DS2k not the earlier issue about DS1k.
You must have missed following this link in the OP:
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777 (https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777)

Yep but I believe also prior to the update which resolved it to the point where it behaved normally.

Buds investigation was on what was left behind after the update.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on May 25, 2016, 06:26:08 pm
It was discussed on page 4 of this thread - about DS2k not the earlier issue about DS1k.
You must have missed following this link in the OP:
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777 (https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777)

Yep but I believe also prior to the update which resolved it to the point where it behaved normally.

Buds investigation was on what was left behind after the update.
I ask you how can a FW update fix a PLL design error, it can't, it only masks the problems it creates.

Buds investigation follows on from what was discovered in the DS1054Z WITH a DS2072A and confirms there's been an error in design, so bad that the PLL manufacturers datasheets layout recommendations appear to have been totally ignored.

Look, all manufactures make mistakes and there's many examples in threads here, this is just another one.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 06:35:51 pm
It was discussed on page 4 of this thread - about DS2k not the earlier issue about DS1k.
You must have missed following this link in the OP:
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777 (https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777)

Yep but I believe also prior to the update which resolved it to the point where it behaved normally.

Buds investigation was on what was left behind after the update.
I ask you how can a FW update fix a PLL design error, it can't, it only masks the problems it creates.

Buds investigation follows on from what was discovered in the DS1054Z WITH a DS2072A and confirms there's been an error in design, so bad that the PLL manufacturers datasheets layout recommendations appear to have been totally ignored.

Look, all manufactures make mistakes and there's many examples in threads here, this is just another one.

Yep a firmware upgrade _can_ resolve a PLL error. I know this because I just built one and the relationship between the physical components and the settings was important enough to make the difference between not locking, locking with massive spurs, and locking with minimal spurs. (that was the best I could do on that board because I ignored the manufacturers advice, new PCB on the way :) )

I completely agree with your second point - they screwed up. But Keysight screwed up too, the only difference was that they detected their screwup and charged $2k to fix it...

But my original point stands -  at least for the DS2k it actually doesn't seem to matter. No-one has yet been able to explain _why_ it doesn't matter.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: tautech on May 25, 2016, 06:50:29 pm
It was discussed on page 4 of this thread - about DS2k not the earlier issue about DS1k.
You must have missed following this link in the OP:
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777 (https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777)

Yep but I believe also prior to the update which resolved it to the point where it behaved normally.

Buds investigation was on what was left behind after the update.
I ask you how can a FW update fix a PLL design error, it can't, it only masks the problems it creates.

Buds investigation follows on from what was discovered in the DS1054Z WITH a DS2072A and confirms there's been an error in design, so bad that the PLL manufacturers datasheets layout recommendations appear to have been totally ignored.

Look, all manufactures make mistakes and there's many examples in threads here, this is just another one.

Yep a firmware upgrade _can_ resolve a PLL error. I know this because I just built one and the relationship between the physical components and the settings was important enough to make the difference between not locking, locking with massive spurs, and locking with minimal spurs. (that was the best I could do on that board because I ignored the manufacturers advice, new PCB on the way :)
Well we learn something every day....thanks.
Do consider sharing your Yaigol design *moment* in another thread, I'm sure we'll all learn from your experience.  ;)

Quote
I completely agree with your second point - they screwed up. But Keysight screwed up too, the only difference was that they detected their screwup and charged $2k to fix it...
But that's not over yet.....once the word get out more and other user/owners that have had to pay for the fix find out....shit anything could happen, court cases, recalls, hey it's all happened to manufacturers before.  :popcorn:

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 06:59:13 pm
But Keysight screwed up too, the only difference was that they detected their screwup and charged $2k to fix it...
There is a big difference between screwed up design and faulty particular unit. Also, don't forget about that it is Brazil, prices will be 2x+ of the US.
Quote
detected their screwup and charged $2k to fix it...
After warranty has already expired.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 07:12:19 pm

I ask you how can a FW update fix a PLL design error, it can't, it only masks the problems it creates.

Buds investigation follows on from what was discovered in the DS1054Z WITH a DS2072A and confirms there's been an error in design, so bad that the PLL manufacturers datasheets layout recommendations appear to have been totally ignored.

Look, all manufactures make mistakes and there's many examples in threads here, this is just another one.

Yep a firmware upgrade _can_ resolve a PLL error. I know this because I just built one and the relationship between the physical components and the settings was important enough to make the difference between not locking, locking with massive spurs, and locking with minimal spurs. (that was the best I could do on that board because I ignored the manufacturers advice, new PCB on the way :)
Well we learn something every day....thanks.
Do consider sharing your Yaigol design *moment* in another thread, I'm sure we'll all learn from your experience.  ;)

Yes I have been thinking about that. I probably will once the new board arrives and I can show some progress.
It was a bit of a journey which started at  'complete disaster' and made it to 'OMG it kinda works' :)

Quote
Quote

I completely agree with your second point - they screwed up. But Keysight screwed up too, the only difference was that they detected their screwup and charged $2k to fix it...
But that's not over yet.....once the word get out more and other user/owners that have had to pay for the fix find out....shit anything could happen, court cases, recalls, hey it's all happened to manufacturers before.  :popcorn:


Agree, that one will be interesting to watch.

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 07:20:47 pm
But Keysight screwed up too, the only difference was that they detected their screwup and charged $2k to fix it...
There is a big difference between screwed up design and faulty particular unit.

Yep, but which one is it ??

Quote
detected their screwup and charged $2k to fix it...
After warranty has already expired.
[/quote]

Yes, but that is on a 2.8k scope. Which is not commensurate with an A brand supplier.
If you have to throw away your scope and buy a new one when it breaks then there is no point buying A brand gear.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 07:39:14 pm
Yes, but that is on a 2.8k scope. Which is not commensurate with an A brand supplier.
If you have to throw away your scope and buy a new one when it breaks then there is no point buying A brand gear.
Not $2.8k if bought in Brazil. You don't understand how bad it is. Even in EU which is not that bad at all, prices usually are much higher. Though often are comparable for Keysight particularly as for now, after EUR exchange rate started to suck a lot but Keysight pricing in EUR seems not changed much.
Translated from newark/element14 website http://www.newark.com/brazil-direct-ship (http://www.newark.com/brazil-direct-ship)
Quote
2- Taxes which focuses and how to calculate?
Import Tax: 60% of the Customs Valuation (Customs Value = the value of goods sum + shipping)
ICMS: on average 18%, varying according to the State
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: hendorog on May 25, 2016, 08:12:10 pm
Wow, those taxes are really bad!!

We have 15% + ~$60 for most items I have imported, and I think that is too much.
Can't do much about exchange rate unfortunately. Our exchange rate was quite favourable against USD too, but now it is not good.



Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on May 25, 2016, 10:21:40 pm
There is a big difference between screwed up design and faulty particular unit. Also, don't forget about that it is Brazil, prices will be 2x+ of the US.
Quote
detected their screwup and charged $2k to fix it...
After warranty has already expired.

Warranty aside, this really looks like some sort of serious design defect. Keysight could be in big trouble if more people read this thread and say, "That happened to me, too!".
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 10:50:43 pm
There is a big difference between screwed up design and faulty particular unit. Also, don't forget about that it is Brazil, prices will be 2x+ of the US.
Quote
detected their screwup and charged $2k to fix it...
After warranty has already expired.

Warranty aside, this really looks like some sort of serious design defect. Keysight could be in big trouble if more people read this thread and say, "That happened to me, too!".
Seriously? PLL fault was not a design defect. All it was unlucky to receive such a scope and not test it in reasonable time period. And WTF Keysight out of warranty discussion is doing in the Rigol tread.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on May 25, 2016, 11:04:47 pm
Warranty aside, this really looks like some sort of serious design defect. Keysight could be in big trouble if more people read this thread and say, "That happened to me, too!".
Seriously? PLL fault was not a design defect. All it was unlucky to receive such a scope and not test it in reasonable time period. And WTF Keysight out of warranty discussion is doing in the Rigol tread.
The 'scope was tested, placed in storage for a while, then refused to boot.

If the firmware is somehow being corrupted (for whatever reason, including "putting it in storage for three months") then that's a design defect.

Keysight has already admitted they've changed the firmware in more recent models so it's easier to re-flash it if it fails. That sounds to me like they've seen a problem.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 25, 2016, 11:12:48 pm
Warranty aside, this really looks like some sort of serious design defect. Keysight could be in big trouble if more people read this thread and say, "That happened to me, too!".
Seriously? PLL fault was not a design defect. All it was unlucky to receive such a scope and not test it in reasonable time period. And WTF Keysight out of warranty discussion is doing in the Rigol tread.
The 'scope was tested, placed in storage for a while, then refused to boot.

If the firmware is somehow being corrupted (for whatever reason, including "putting it in storage for three months") then that's a design defect.

Keysight has already admitted they've changed the firmware in more recent models so it's easier to re-flash it if it fails. That sounds to me like they've seen a problem.
Maybe you should read it one more time? His scope with no boot issue was replaced IIRC after about 2.5 years. He briefly tested the replacement and put it into storage. Then when 3 year warranty already passed, he started to use the scope, after 2 hour heat up he got PLL error. Now his scope fails after about 40 minutes. Nothing to do with no boot issue which BTW is honored with free repair even after warranty has ended.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on May 25, 2016, 11:28:34 pm
Maybe you should read it one more time?

Maybe I should, it's hard to remember which of all the failed Keysights 'we're actually talking about.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 26, 2016, 02:38:37 am
Maybe you should read it one more time?

Maybe I should, it's hard to remember which of all the failed Keysights 'we're actually talking about.
:palm: Your will to bash everyone except holy Rigol is just amazing. I'm talking about The Keysight form Brazil (link you posted in this tread). Get your facts right, before blaming some manufacturer for commited crimes.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on May 26, 2016, 02:40:31 am
I'm talking about The Keysight form Brazil (link you posted in this tread).

I'm just amazed you're defending Keysight here. If it was Rigol doing this you'd be going in with both guns blazing.

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on May 26, 2016, 02:45:42 am
I'm talking about The Keysight form Brazil (link you posted in this tread).

I'm just amazed you're defending Keysight here. If it was Rigol doing this you'd be going in with both guns blazing.
I'm amazed I need to defend Keysight in Rigol tread because someone writes off topic BS in multiple treads.
I personally found some Keysight manufacturing fault in U1272A meter and created a tread in the past. And few people found the same issue in their meters (all got exchanged even without returning first).
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: pascal_sweden on July 30, 2016, 08:12:00 pm
Is there any overall write up or summary about the Yaigol project?

I am looking for something in the following structure:

1) Initial problem detected that seem to indicate a design issue
2) Investigation about the design issue
3) Confirmation about the actual design issue
4) Current impact of the design issue
5) Current firmware workaround for the design issue
6) Actual hardware fix for the design issue
7) Improved results after the design issue has been fixed in hardware
8) Scopes that are affected: Rigol DS1054Z, Rigol DS2072A?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: outremer on July 31, 2016, 01:28:40 pm
 :clap:  Hi all !

I spent hours reading this thread, redirected by tautech. I was impressed by the work of Bud. I'am planning to purchase a DS2202A. After analysing  the various contributions I came to the conclusion that the scope should just work according to its specs no matter if the spectral purity of its PLL output is perfect or not. If a firmware upgrade fixes the issue I will not look further. Poeple driving a Volkswagen diesel car have been more abused although the victim is the environment. This story is also good example to show how software gets more and more the determining factor in correcting design errors. See how the faulty  mirror of telescope Hubble was "repaired" (shoud I say repolished ?) with a bunch of code lines).

Regards, Phil FM5GB.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: German_EE on July 31, 2016, 06:11:08 pm
The Hubble Telescope was repaired using a module called COSTAR which is about the size of a baby grand piano. Applying this fix required design, construction, delivery by Space Shuttle and two astronauts carrying out an eight hour spacewalk.

A bit more than "a bunch of code lines"
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Emi on August 01, 2016, 11:22:18 pm
Hi  :D
After reading all these posts i still dont know how should  i test My ds2072 in order To confirm its "goodness " or not.
I put in a 1k Sine and its perfect and stable..so with 1mhz, 10, 100 and over 450 mhz...
Ive seen a complex  433 mhz Fm/pcm modulated signal from a radio remote control with stock probes too..perfecltly displayed. .i rally cant be disappointed with this stuff. .
 8)
How Can i really test all the above described  issues?
( i Mean at home .. without specific Lab instruments. .)

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on August 01, 2016, 11:44:55 pm
the scope should just work according to its specs no matter if the spectral purity of its PLL output is perfect or not.

Exactly.

It's a clock. The only important thing about a clock is that it's regular.

The PLL design is messed up, but... it doesn't affect the results. That's probably why nobody at Rigol noticed it during testing. :-//

Ive seen a complex  433 mhz Fm/pcm modulated signal from a radio remote control with stock probes too..perfecltly displayed.
How Can i really test all the above described  issues?

Maybe they're not really issues. Maybe it's just people on a witch hunt.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: German_EE on August 02, 2016, 12:18:40 am
"It's a clock. The only important thing about a clock is that it's regular."

Not true.

If an ADC is driven with a clock that has a poor phase noise then this will affect the output, the same applies to a DAC or a DDS chip.

If a clock signal has variations in amplitude then, in marginal cases, some of the clock signals will be missed leading to timing errors

If a clock is out of phase with the rest of the circuitry then this can lead to race conditions and data being latched at the wrong point

So, a good clock needs to be stable in frequency, have low phase noise, constant amplitude and be coherent with other signals on the PCB.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on August 02, 2016, 12:29:53 am
So, a good clock needs to be stable in frequency, have low phase noise, constant amplitude and be coherent with other signals on the PCB.

While all of that is true, nevertheless a DSO is just a tool. As long as it performs it's end tasks capably and without appreciable error - allowing me to do my job - that's all that matters. My hammer has a loose head, yet still I can pound nails with it.

People have been buying inexpensive test instruments with all kinds of wonky circuitry (overclocked ADCs, etc) and using it to get their jobs done for many years already.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Monkeh on August 02, 2016, 12:32:35 am
My hammer has a loose head, yet still I can pound nails with it.

And one day that head's going to come off and cause you grief. :)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on August 02, 2016, 12:39:48 am
And one day that head's going to come off and cause you grief. :)

It would only cause you grief if you were naive enough to believe it would never come off.  ;)

I have to think the OP didn't do much, if any, research into the level of design, manufacturing, testing, and quality components inherent in cheap Chinese test equipment before he bought his DSO. I don't buy a $1 hammer and expect a $20 one.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on August 02, 2016, 02:15:29 am
My hammer has a loose head, yet still I can pound nails with it.

And one day that head's going to come off and cause you grief. :)

That's the problem with analogies - people can look for holes in the analogy instead of sticking to the main discussion.

A better analogy would be a hammer with a tiny crack somewhere deep inside the metal. It's imperfect, yes, but it hammers things just fine and there's no reason to believe it will ever do otherwise.

PS: If you own a hammer, how do you know it's perfectly cast? Does it scare you that there might be something wrong with it? Something down inside...  :scared:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rstofer on August 02, 2016, 03:30:50 am
Is there any overall write up or summary about the Yaigol project?

I am looking for something in the following structure:

1) Initial problem detected that seem to indicate a design issue
2) Investigation about the design issue
3) Confirmation about the actual design issue
4) Current impact of the design issue
5) Current firmware workaround for the design issue
6) Actual hardware fix for the design issue
7) Improved results after the design issue has been fixed in hardware
8) Scopes that are affected: Rigol DS1054Z, Rigol DS2072A?

That's a lot to expect for a $400 scope!

There are two of these threads running and, after reading both, I suspect there may be some slight issues at the edges.  In other words, with stuff I am never going to use.  So I simply don't care!  Can I get 4 wiggles on the screen that bear some semblance to reality?  Sure!  And that's all I need.

There are about 4 people on the forum who are absolute Rigol haters.  No other way to describe them.  But here's the thing:  They won't sell off their Rigol scopes and buy something better.  They just continue to use the thing while simultaneously bashing it.  What's the sense in that?  They could dump the thing for $300 and spend the proceeds plus another $1000 or so and get a scope that's twice as good (maybe) at 3 times the price of the original Rigol.

Here's another thing:  You aren't going to get a $10,000 scope for $400.  If the minor (trivial) failings of the 1054Z will eventually cause you grief, buy something else.  Don't even look at the 1054Z.  Or any other Chinese scope, for that matter.  And don't expect that Rigol will ever fix the bugs.  That way you won't be disappointed when they don't.

It is what it is and it will never be any better than it is today.  If you keep that in mind, you won't be disappointed.  Or, throw in a whole lot more money and buy something better.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: nctnico on August 02, 2016, 03:45:32 am
People have been buying inexpensive test instruments with all kinds of wonky circuitry (overclocked ADCs, etc) and using it to get their jobs done for many years already.
That may be true but how many people will say 'gosh I wish I had bought this way better tool years ago because it is such a joy to use' after they got a quality tool instead of a low cost make-do POS? I'm sure the answer is many and it doesn't take a whole lot more money to buy a decent tool instead of something crappy. People just don't know what they don't know and often get blinded by what seems to be a good deal on paper but isn't in reality.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on August 02, 2016, 04:01:11 am
People just don't know what they don't know and often get blinded by what seems to be a good deal on paper but isn't in reality.

True, but then you have to ask yourself how much of the fault lies with the buyer? It doesn't take much research to see what the level of quality, workmanship, firmware development, support, etc. *can* be with Chinese-made test instruments. I would hope people without much money to spend do some research when spending a few hundred bucks on something.

And honestly, if you don't try to save every last little penny, you can usually give yourself a bit of 'buyer protection'. I personally never bought any Chinese-made test instrument that I couldn't return (except, of course, for things that cost less than € 50), so when I bought my first couple of Chinese DSOs - a Rigol and a Owon - I bought them from European distributors, which allowed me to return both of them for just shipping costs. Sure, I lost some money - but I was much happier with the DSO that I eventually kept.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rstofer on August 02, 2016, 04:08:14 am
People have been buying inexpensive test instruments with all kinds of wonky circuitry (overclocked ADCs, etc) and using it to get their jobs done for many years already.
That may be true but how many people will say 'gosh I wish I had bought this way better tool years ago because it is such a joy to use' after they got a quality tool instead of a low cost make-do POS? I'm sure the answer is many and it doesn't take a whole lot more money to buy a decent tool instead of something crappy. People just don't know what they don't know and often get blinded by what seems to be a good deal on paper but isn't in reality.

And years later, if they really need an upgraded model, they sell off their lesser model and buy the newest thing on the market which will be far better than was available at the time of the first purchase (newer technology, larger screen, more measurements, etc).  In the meantime, they have used the scope for the difference between the buy and sell price.  Not all that much, I suspect.

Or, they never need an upgraded model.  In my view, it's better to get something and get started.  Interests change and there is no point in being overinvested in equipment. 

Yes, I do wish I had bought the Ferrari instead of the Porsche back when I was young.  That I might not have survived the experience is beside the point.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on August 02, 2016, 01:05:24 pm
People have been buying inexpensive test instruments with all kinds of wonky circuitry (overclocked ADCs, etc) and using it to get their jobs done for many years already.
That may be true but how many people will say 'gosh I wish I had bought this way better tool years ago because it is such a joy to use' after they got a quality tool instead of a low cost make-do POS?

a) The DS1054Z certainly isn't a "make-do POS".
b) At what price level do oscilloscopes stop being "make-do POS", in your opinion?

and

c) I really hope you never buy anything in real life, because there's always something better for more money. Always a better car, always a better house, always better furniture, always better clothes, always a better computer, always a bigger boat... how will you ever be satisfied?

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on August 02, 2016, 01:09:03 pm
There are about 4 people on the forum who are absolute Rigol haters.  No other way to describe them.  But here's the thing:  They won't sell off their Rigol scopes and buy something better.

Yep, it's weird how they all own Rigols. It would be easy to sell them and buy $400 GW-Insteks instead, right? They'd probably get $300 if they sold their Rigols. So much suffering for the sake of $100, does it make sense to anybody?

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: JPortici on August 02, 2016, 03:39:03 pm
But if they didn't have rigols then they would be accused of
- being hypocrite
- not knowing what they talk about
- not keeping up with the update because you know you are comparing your system and you don't know nothing about how is it now do you
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on August 02, 2016, 04:42:21 pm
It's not easy being a Rigol basher...  :popcorn:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on August 02, 2016, 08:35:02 pm
Yep, it's weird how they all own Rigols. It would be easy to sell them and buy $400 GW-Insteks instead, right? They'd probably get $300 if they sold their Rigols. So much suffering for the sake of $100, does it make sense to anybody?

Actually, nctnico feels he got burned by being an early-adopter of the Siglent SDS2000.

Here's the thing: all of the inexpensive DSOs (Rigol, Siglent, Owon, Hantek, etc.) work perfectly fine in most respects, but tend to not work / have some bugs with / lack certain features in some area(s). If you plan on buying any of these DSOs, you have to reckon on the fact that those features / bugs may never get fixed. If those particular features are crucial for the work you do (I think they were in nctnico's particular case with the Siglent): don't believe promises from the manufacturers - look elsewhere for an inexpensive DSO. That's why it's a good idea to give yourself a chance to test any equipment with the option to return it.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rsjsouza on August 02, 2016, 10:23:43 pm
People have been buying inexpensive test instruments with all kinds of wonky circuitry (overclocked ADCs, etc) and using it to get their jobs done for many years already.
That may be true but how many people will say 'gosh I wish I had bought this way better tool years ago because it is such a joy to use' after they got a quality tool instead of a low cost make-do POS? I'm sure the answer is many and it doesn't take a whole lot more money to buy a decent tool instead of something crappy. People just don't know what they don't know and often get blinded by what seems to be a good deal on paper but isn't in reality.
An affordable "POS" can be seen as high quality in the hands of someone that never had access to such gear... Since technology advances at a fast pace, with the consequences for price/features, a purchase decision cannot be dissociated from the offers at the time. In other words, "quality" is very fluidly defined in terms of price, durability, features, bugs, cost of ownership (to name a few). For personal use the price and features have a heavier weight, while for business the durability and cost of ownership are more critical. That is why it is easier to make the statement highlighted when you make money with the tool.

Just to give an example, check my oscilloscope walk of life in this other thread (https://www.eevblog.com/forum/testgear/question-about-analog-oscilloscopes-vs-digital-oscilloscopes/msg968187/#msg968187). Given the current prices of used DSOX3000 oscilloscopes from Keysight, probably my decision to purchase the DS4014 would be different.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: scummos on September 02, 2016, 07:51:44 am
Very nice analysis and thanks for the writeup -- it was a fun read. It's indeed quite ridiculous Rigol doesn't even have a Lock indicator monitoring in place -- even my $100 hobby project displays an error message if the PLL fails to lock.

Here's the (in my opinion) interesting question, though: does this actually affect the scope's performance in a relevant way? Of course your ADC spectrum shouldn't look like that. But 50 kHz bandwidth over 1 GHz clock is something like < 1e-4 error. Most situations I can think of wouldn't have a single pixel changed in the signal display on the screen from that fault ...
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on September 02, 2016, 07:32:43 pm
does this actually affect the scope's performance in a relevant way?

Nope.

(And I guess this is why the "problem" got past the development stage - there's nothing wrong on screen).
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on September 02, 2016, 08:25:53 pm
But 50 kHz bandwidth over 1 GHz clock is something like < 1e-4 error. Most situations I can think of wouldn't have a single pixel changed in the signal display on the screen from that fault ...
Yes it does, look at the DS1054Z video, with the quality of the clock in this particular BUD's scope, the same jitter problem should be present (but no SW fix).
https://www.youtube.com/watch?v=K1IJH9aJvgE (https://www.youtube.com/watch?v=K1IJH9aJvgE)
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: scummos on September 03, 2016, 02:20:19 am
The screenshot in Bud's PDF has a span of 50 kHz. This one has 4 MHz ... with 4 MHz spread, you are .25% off, I can imagine you can see that. But yeah, you're right -- it could cause this kind of problem
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on September 03, 2016, 02:33:50 am
The screenshot in Bud's PDF has a span of 50 kHz. This one has 4 MHz ... with 4 MHz spread, you are .25% off, I can imagine you can see that. But yeah, you're right -- it could cause this kind of problem

As well as being a different model of DSO.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on September 03, 2016, 03:07:52 am
As well as being a different model of DSO.
It's irrelevant, same clock stability issue will cause the same jitter problem on different models.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: marmad on September 03, 2016, 03:09:25 am
As well as being a different model of DSO.
It's irrelevant, same clock stability issue will cause the same jitter problem on different models.

It's relevant since many of us with DS2000s have measured no clock instability issue whatsoever (read thread). IIRC, it was much more common (and much worse) in the DS1000Z, the model in the video you posted.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: wraper on September 03, 2016, 03:18:45 am
As well as being a different model of DSO.
It's irrelevant, same clock stability issue will cause the same jitter problem on different models.

It's relevant since many of us with DS2000s have measured no clock instability issue whatsoever (read thread). IIRC, it was much more common (and much worse) in the DS1000Z, the model in the video you posted.
The same of you also likely don't have oscillating Vregs. As I posted before, my scope uses different flavor of 1117 and there is no oscillation.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: RoGeorge on October 21, 2016, 04:03:11 am
This post is just to easily follow the subject.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Fungus on October 21, 2016, 04:19:49 am
This post is just to easily follow the subject.

What on earth for? It's just a bunch of sourpusses who can't actually demonstrate any effect on screen.

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Bud on October 21, 2016, 09:40:21 am
This thread is about proper engineering, not about Walmart shopping.

Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: madires on October 21, 2016, 10:34:43 pm
This post is just to easily follow the subject.

What on earth for? It's just a bunch of sourpusses who can't actually demonstrate any effect on screen.

He posted that text in 8 threads. :-//
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rch on October 21, 2016, 10:48:46 pm
This post is just to easily follow the subject.

What on earth for? It's just a bunch of sourpusses who can't actually demonstrate any effect on screen.

He posted that text in 8 threads. :-//

Perhaps he hasn't noticed the 'notify' button?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: Zbig on October 21, 2016, 11:05:51 pm
This post is just to easily follow the subject.

What on earth for? It's just a bunch of sourpusses who can't actually demonstrate any effect on screen.

He posted that text in 8 threads. :-//

Perhaps he hasn't noticed the 'notify' button?

He's actually been advised to do just that by a seasoned EEVBlog member: https://www.eevblog.com/forum/chat/show-unread-messages-but-filter-only-the-topics-where-i-wrote-something/msg1052861/#msg1052861 (https://www.eevblog.com/forum/chat/show-unread-messages-but-filter-only-the-topics-where-i-wrote-something/msg1052861/#msg1052861) :palm:
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on October 22, 2016, 06:32:43 am
The notify button will email you new replies, but won't add the thread to the new replies page. Unfortunately, you have to reply to a thread to have the forum track it on the new replies page.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: rch on October 22, 2016, 09:15:44 am
The notify button will email you new replies, but won't add the thread to the new replies page. Unfortunately, you have to reply to a thread to have the forum track it on the new replies page.

The answer is to try very hard to say something relevant to the thread.  People may not think it very profound, but at least they may not spot what one is up to!
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: bitseeker on October 22, 2016, 10:30:30 am
The answer is to try very hard to say something relevant to the thread.  People may not think it very profound, but at least they may not spot what one is up to!

Certainly.

To that end, since the conclusion of this investigation, has anyone else opened up a newer hardware version of a 2000-series scope for comparison?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: RoGeorge on September 11, 2017, 06:22:54 am
There were some questions about the Rigol DS1000Z PLL in another thread, and most of the arguments were coming from this topic, so I read the PDFs posted at the beginning, then the whole thread, and decided to ask here, even if it's been a while since the last post.

By the way, very good findings and well documented, thank you very much for posting them, Bud.

For testing my DS1054Z jitter at 5us distance from the trigger point, I used the latest firmware (which is supposed to fix the PLL issue in software by using better values for programming the PLL), and indeed at 5 us distance the Jitter is not visible any more on the screen.

Still, if I increase the distance from the trigger point long enough, there still is some jitter, and the jitter is apparently increasing linearly with the distance in time from the trigger point.

I measured the jitter by setting the display to memorize the trace on the screen for the last 10 seconds, and try to guess the best spread in time of the edges by averaging 5 different captures. Both instruments were on for a couple of hours at constant temperature before measuring. Here are some values measured with a square signal from a Rigol DS4102 DDS (that is supposed to have +/- 2ppm frequency accuracy, and a max jitter of 500ps according to its specs) using a 50 ohms cable and an external terminator at the oscilloscope's BNC.

As can be seen in the attached captures, the jitter is increasing almost linearly with the time distance from the sync point. Why is that? Isn't the PLL jitter supposed to be random and independent of the test signal, so the jitter of the displayed test edges wouldn't accumulate with the distance from the trigger point?

The PLL is trying to sync with the internal oscillator, which is running continuously and independently from the test signal, so if the PLL jitter is randomly distributed, then I expect to see on the screen the same jitter for any edge of the test signal, no matter how far from the trigger point is the displayed test edge.

Why does the displayed jitter of the edges from the test signal increases (almost linearly) with the distance (in time) from the trigger moment?
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: TimNJ on September 14, 2017, 12:35:16 am
There were some questions about the Rigol DS1000Z PLL in another thread, and most of the arguments were coming from this topic, so I read the PDFs posted at the beginning, then the whole thread, and decided to ask here, even if it's been a while since the last post.

By the way, very good findings and well documented, thank you very much for posting them, Bud.

For testing my DS1054Z jitter at 5us distance from the trigger point, I used the latest firmware (which is supposed to fix the PLL issue in software by using better values for programming the PLL), and indeed at 5 us distance the Jitter is not visible any more on the screen.

Still, if I increase the distance from the trigger point long enough, there still is some jitter, and the jitter is apparently increasing linearly with the distance in time from the trigger point.

I measured the jitter by setting the display to memorize the trace on the screen for the last 10 seconds, and try to guess the best spread in time of the edges by averaging 5 different captures. Both instruments were on for a couple of hours at constant temperature before measuring. Here are some values measured with a square signal from a Rigol DS4102 DDS (that is supposed to have +/- 2ppm frequency accuracy, and a max jitter of 500ps according to its specs) using a 50 ohms cable and an external terminator at the oscilloscope's BNC.

As can be seen in the attached captures, the jitter is increasing almost linearly with the time distance from the sync point. Why is that? Isn't the PLL jitter supposed to be random and independent of the test signal, so the jitter of the displayed test edges wouldn't accumulate with the distance from the trigger point?

The PLL is trying to sync with the internal oscillator, which is running continuously and independently from the test signal, so if the PLL jitter is randomly distributed, then I expect to see on the screen the same jitter for any edge of the test signal, no matter how far from the trigger point is the displayed test edge.

Why does the displayed jitter of the edges from the test signal increases (almost linearly) with the distance (in time) from the trigger moment?

I haven't been following this thread nor am I an expert on PLLs, but perhaps you are witnessing some level of frequency modulation and not "jitter"?

In a control loop with frequency control, like in a switchmode power supply, this behavior is common. Let's say the modulating signal is sinusoidal. That would mean that the PLL clock signal would constantly be sweeping up and down from fmin to fmax. In a digital scope, when you are triggered on the rising edge of a clock signal, to the left and right of the trigger point, you see the "past" and "future" of the signal. Now, keeping the trigger point locked down, superimpose fmin onto fmax. You will see as you move farther away from the trigger point, the difference in time (phase difference) between the clock edges will get greater and greater. This phase difference is continuously compounded as you move away from the trigger point. I attached a little picture to help illustrate.

I'm not entirely sure if that's what you're seeing but that's what it sounds like to me.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: RoGeorge on September 17, 2017, 07:17:43 pm
Yes, it could be some kind of frequency modulation.

Still, on the oscilloscope's screen, the edges are jumping around a middle position. The jumping seems pretty random to me, it doesn't look like a continuous drift or a modulation, but I didn't made any statistics, so I might be wrong. Next time I will try to record the screen, and post it here. My experience with stable oscillators is zero, it might be just normal to see an edge randomly jumping inside a 100ns range window when looking at 1 second later after the trigger point, I don't know.

I also suspect that the oscilloscope might not use a circular buffer for storing the ADC's samples (which would be crazy, but who knows), and for delays longer than 24ms (max scope's memory is 24 million samples, at a sample rate of 1Gs/s that would be 24ms) the scope is just waiting for the required delay without sampling, then start sampling and memorizing. If this is true, and the waiting delay is calculated using the reference oscillator (25MHz) and not the PLL (1GHz), that might make the seen "jitter" to accumulate for longer delays.

For my own curiosity, for the next step I want to save all 24 Msamples in the PC (for many times) and do some Fourier analysis. The hope here is to clarify if what is seen on the screen is because of a jitter, a drift, a frequency modulation or maybe something else.

For the next measurements, I will try to use the sync output from the generator, as Teneyes PM'ed me, in the hope that the edges from the sync output will be faster then the edges of the signal output, and this will reduce the oscilloscope's trigger jitter. Trigger jitter should not accumulate with the viewing delay, but the more stable, the better.

Also, I searched about jitter accumulation in PLLs, and found a few PDFs online, but didn't have the time to parse them, so I'm not sure yet if the jitter accumulation described in those PDFs is applicable here.

TL;DR
Just to be clear: The 5us PLL jitter bug from a couple of years ago was fixed long time ago. That bug is not present any more in my DS1054Z.

What I am testing here is just because I want to have a better understanding about PLLs in general.
Title: Re: Project Yaigol: Fixing Rigol scope design problems.
Post by: RoGeorge on September 26, 2017, 11:10:42 am
Since I'm not sure this is related to this thread, I am posting the new measurements in a new topic:
https://www.eevblog.com/forum/testgear/rigol-dg4102-and-ds1054z-skew-and-accumulating-jitter/msg1309844/ (https://www.eevblog.com/forum/testgear/rigol-dg4102-and-ds1054z-skew-and-accumulating-jitter/msg1309844/)