Author Topic: Project Yaigol: Fixing Rigol scope design problems.  (Read 83310 times)

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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #200 on: March 30, 2016, 03:21:00 am »
Tim got it right or almost right, and a few other people were close. It could be seen that the mv/Div was set very low, 500uV/ in one shot and 5mV/ in the other, but there was no trace noise in the shots, look how noise-free the waveform is.



In Part 5 I said the variable bandwidth VGA in the front-end is responsible for generating most of the noise in the path. Noise-free waveforms in the screenshots with such small mv/Div could only be obtained if to bypass most of the input stage and inject the signal into the ADC buffer. It was too much problem to get the signal right into the ADC pins, it was easier to do it with the ADC buffer stage as shown in the following picture.



I unsoldered the two SMT resistors (they are two zero Ohm jumpers) located near the VGA and that gave me access to the LMH6552 ADC buffer input. hooked up a RF balun to it to convert differential input into single ended input, with a pigtail microcoax soldered to the other end of the balun.



I could then perform sweeps and do bandwidth measurements of the ADC buffer + ADC, lets take a look again what I posted in Part 5:



We are looking at the blue line which is the ADC buffer + ADC transfer function. In fact it had gain so the chart was normalized to the maximum gain point which occurred at around 300MHz with 5dB gain. Therefore if we consider the leftmost end of the blue line to be 0dB, the -3dB point to the right of it and relative to it would be around 800...850MHz (the blue line). So technically this part of the signal path is capable of 800MHz bandwidth, and that was what you saw in the screenshots with a sinewave and raise time test.

I recall doing a few sweeps and if I remember correctly the scope triggered up to 600MHz. Above that it rolled but I could stop it and see the waveform up to 800MHz (with 2GS/ sample rate, single channel mode). So basically the capability is there but is crippled by the VGA bandwidth limit. Technically the VGA SPI bus could be hacked, commands intercepted and corrected so in Full bandwidth mode it could be set to say 600MHz, so what you get is  a 500MHz scope for almost no extra money. The problem however is with highjacking the VGA SPI bus tracks, doing this would require unsoldering the LMH6518 VGA and perhaps fitting it on a small PCB and retrofit that PCB back to where the VGA was. Too much trouble, though in theory can be done. May be I would have done it, had I not decided by the time I will not keep the scope. Also, I had not thoroughly tested the scope in all modes with this, beside the FFT which still worked correctly. I think the frequency counter became shaky and gave incorrect readings above 450MHz or so. Anyway, this may be an interesting info for a determined person to explore more.

So, [Dave mode] if you liked this info, give it a thumbs up, that always helps [/Dave mode]  :D

« Last Edit: March 30, 2016, 03:29:10 am by Bud »
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #201 on: March 30, 2016, 04:48:19 am »
Actually a quick and dirty method would be to use the above schematic trick with a 1:4 balun and feed its input coax to may be the back panel or to one channel's BNC on the front panel of the scope, The input stage of one channel can be sacrificed for that if there is a desperate need in a higher bandwidth. Scope V/Div settings would not work in this case for that channel and the input must be kept less than 100mV RMS to not overload the ADC buffer.

A variation of it could be reusing the attenuator stage and may be reusing everything else and skipping the VGA. That would give possibility to change V/Div and perhaps vertical position adjustment. Still, V/Div would not be accurate because some of gain adjustment occurs in the VGA via the SPI bus control.   :blah:
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Online hendorog

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #202 on: March 30, 2016, 06:08:11 am »
What do you think would happen if the VGA was able to be reset - i.e. remove power and then restore it.

If I read it correctly its power on state according to the datasheet is Full bandwidth, low gain and no attenuation.
 

Offline nctnico

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #203 on: March 30, 2016, 08:52:31 am »
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline exe

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #204 on: March 30, 2016, 08:58:47 am »
So basically the capability is there but is crippled by the VGA bandwidth limit.

That's why I always want source codes at hand :(. It would be just a few lines code changed to "unlock" the performance. It's not just about scopes, in general a lot of hardware is capped by software.

So, [Dave mode] if you liked this info, give it a thumbs up, that always helps [/Dave mode]  :D

Thumbs up! :D
 

Offline T3sl4co1l

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #205 on: March 30, 2016, 11:19:48 am »
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!

Aliasing is desirable for an oscilloscope.

With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

Tim
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Offline rch

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #206 on: March 30, 2016, 11:31:52 am »
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!

Aliasing is desirable for an oscilloscope.

With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

Tim


I remember when that was the only way to make a 1GHz 'scope!
 

Offline Alex Eisenhut

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #207 on: March 30, 2016, 11:48:18 am »
The problem with bypassing the VGA (and other bandwidth limiting devices) is that you'll get a whole lot of aliasing with any signal which is not a sine wave. In other words: you need filtering in the front end!

Aliasing is desirable for an oscilloscope.

With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

Tim

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Offline exe

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #208 on: March 30, 2016, 12:26:35 pm »
Tektronix 547 + 1S1 plugin.

Is there any plugin for storing and navigating waveforms?  ;D
 

Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #209 on: March 30, 2016, 01:40:10 pm »
With suitable timing, it can be harnessed to obtain equivalent time sampling.  Imagine over 1GHz bandwidth from a $400 scope!

DS2072a price is $839 or something.
« Last Edit: March 30, 2016, 01:54:24 pm by Bud »
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #210 on: March 30, 2016, 01:52:02 pm »
What do you think would happen if the VGA was able to be reset - i.e. remove power and then restore it.

If I read it correctly its power on state according to the datasheet is Full bandwidth, low gain and no attenuation.

But cycling the power may also reset the DC offset calibration (im still not sure if some or all of it done by the VGA)

I am now thinking that in fact you only need to highjack the Chip Select line, the Data abd Clock perhaps could be simply paralleled with the scope bus. In which case should be possible to leave the VGA on the board.


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Offline ghulands

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #211 on: March 30, 2016, 06:53:37 pm »
I'm looking to get a DS4024 and was curious if anyone who has one has checked to see if it too has this as well.
 

Offline el_dooderino

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #212 on: March 30, 2016, 07:23:43 pm »
Thanks for doing this! Really enlightening. Besides the obvious improvement of the clock spectrum, do you notice a difference on captured waveforms? Perhaps a lower noise floor or less jitter on captured signals?
 

Online hendorog

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #213 on: March 30, 2016, 07:28:16 pm »
I'm looking to get a DS4024 and was curious if anyone who has one has checked to see if it too has this as well.

Connor Wolf did a teardown of one here:
 
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Offline ghulands

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #214 on: April 01, 2016, 04:21:31 pm »
I'm looking to get a DS4024 and was curious if anyone who has one has checked to see if it too has this as well.

Connor Wolf did a teardown of one here:


Thanks for the link. I couldn't see the PLL circuit in that video, but I think I did find it in another one of his videos

https://youtu.be/MbWz8yB_vTQ?t=701

It's not the sharpest image that i grabbed from the video. But i think this might be it. Can anyone confirm?
 

Online Fungus

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #215 on: April 01, 2016, 07:21:21 pm »
Thanks for doing this! Really enlightening. Besides the obvious improvement of the clock spectrum, do you notice a difference on captured waveforms? Perhaps a lower noise floor or less jitter on captured signals?

This.

Does the 'fix' make the slightest difference to the performance of the 'scope?
 

Online EEVblog

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #216 on: May 14, 2016, 08:36:22 am »
Can't believe I haven't seen this thread!
The forum is just too big I guess...
 

Offline krivx

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #217 on: May 14, 2016, 09:15:19 am »
Can't believe I haven't seen this thread!
The forum is just too big I guess...

It seems like pretty good video material...
 

Offline kcbrown

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #218 on: May 17, 2016, 05:08:44 pm »
Quite some time back, in a different thread, I wrote:

In regards to your hardware issue guess, it well may be the case. I have opened my 2072a to fix the ADC clock problem and what I found beside that problem was bunch of other hardware related problems all over the board, along and across. In one instance reviewing a circuit that occupied 1 square inch of space on the  PCB I counted 10 design errors! Wrong component selection, wrong design, wrong circuit layout. 10 errors per sq inch,

Have you detailed these errors somewhere, and especially the corrections you'd make to fix the errors you found?   If so, where did you write them up?

If not, why not?   Such an analysis could be immensely useful, or at the very least highly instructive.


Boy, did Bud deliver!!   This is awesome stuff.   MAJOR thumbs up!
 

Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #219 on: May 18, 2016, 04:32:53 am »
Someone posted in a other thread 2000 line is/will be soon discontinued. Good to see that crap go. Until then feel free to spread the word and repost so more people get educated on the meaning of "best bung for the buck".
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Online tautech

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #220 on: May 18, 2016, 04:46:43 am »
Someone posted in a other thread 2000 line is/will be soon discontinued. Good to see that crap go. Until then feel free to spread the word and repost so more people get educated on the meaning of "best bung for the buck".
:scared:
That's not a typo is it?
 :popcorn:
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Offline Circlotron

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #221 on: May 19, 2016, 05:37:05 am »
"best bung for the buck".
Or more realistically "least worst scope for your money".
I've got one. When I don't know what is happening on the inside, most everything looks good on the outside. That's not to excuse sloppy hardware and firmware for a moment, and I wish they were both perfect, but the way I use my scope 99% of the time there are no obvious shortcomings. Having said that, I'm all for uncovering what ought to be improved.
 

Offline bitseeker

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #222 on: May 19, 2016, 06:06:07 am »
It's also worthy to note that Rigol did make improvements/corrections to this and other models and devices since their introduction.
I TEA.
 

Offline kripton2035

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #223 on: May 19, 2016, 06:13:20 am »
the only solution : win a keysight next year !

Offline bitseeker

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #224 on: May 19, 2016, 06:41:34 am »
Yes! I shall enter again. Next time for sure. LOL!
I TEA.
 


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