I was about to start a topic like that. I'm in the market of small signal fets, and I'm looking for those devices with lowest gate capacitance so I can easily drive them by an opamp. The thing is, according to my transistor tester, gate capacitance often doesn't match typical value. Like FDV301N measured 200pf instead of 50pf "typical". The DS provides only typical value. I had same thing with other devices. Like, one device measured 80pf instead of 25 or 30.
Idk how much I can trust transistor tester on that, but it seems for some devices it does display what's close to typical value.
That one is fine, but take note of all the conditions. For VDMOS, Ciss depends on Vds. In fact, in the Vgs < Vgs(th) region, you get a delightfully variable capacitor, albeit not a high-quality one (depending on RG; usually a few ohms though), and a pretty fair voltage range (20Vpp or so) with high linearity.
More specifically, Cgs is ~constant and Cdg varies. You can see this in the plots, Ciss = Crss + a constant, more or less. It's normally a small difference a log plot, but it's there. Downside, the large fixed Cgs rather limits tuning range, of course.
This is probably surprising if your state of knowledge started with lateral (Ciss depends on Vgs, Vgd), or you're inferring from a similar point (in general, MOS capacitors are voltage-dependent, why not MOSFETs?).
It's also funny to me, because a lot of SPICE models even modeled Cdg as dependent on Vgd, even to the point of making a virtual rectifier and dependent capacitor circuit (i.e. on the assumption that C(Vdg) = C(-Vgd)), but nah it's a three-terminal device with Vds biasing it, not Vgd at all. Maybe that was itself a better approximation, or even a whole truth, in older types, which the models were invented for, but then applied to HEXFETs and then trench MOS where it isn't very realistic at all. No idea.
As for the claimed effect, it might not affect small transistors, depending on what design they are; AFAIK, SJ hasn't come to very low voltages yet (it requires a high aspect ratio to work, so if you're making the pillars short (thin depletion region, low voltage rating), they have to be incredibly narrow, but can't be made finer than the tech node feature size), and those are still more or less stock VDMOS, though there are still many incremental developments being made that I don't know about. And old designs that are never updated, aren't, so there's always IRF540 etc. if you need something slow, cheap, modest power, and only mostly nonlinear.
For something like a linear circuit, the stability effect of Crss and Coss variation tends to be stronger, forcing some minimum compensation setting; in contrast, the high gm tends to reduce the impact of Ciss, i.e. perhaps compensation dominates. And consider an R+C at the output to ballast load reactance, if this is something general like an electric load.
Tim
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