EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: leonhart88 on July 13, 2015, 01:40:25 am
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Hi All,
This kind of relates to a previous post/question I had where I was having issues with measuring current consumption of a device I'm working on. I was reading unexpectedly large currents even though I had a large amount of capacitance and the results did not match my simulations. The capacitance I had was supposed to accommodate for large, short current bursts, but they did not seem to be doing anything to help reduce current draw from the source. The device is pulsing two IR LEDs with 400mA each from a 3V regulator.
Just today, I tried moving my storage capacitors closer to the LEDs and it seemed to resolved the issues I was previously seeing. Once I moved the caps, I could see that the current consumption dropped, and things started to match my simulations.
This is what the circuit looked like previously.
(https://www.eevblog.com/forum/projects/pulse-current-capacitor-locationplacement/?action=dlattach;attach=160857;image)
This is what I changed (I realize this has an extra 4.7uF compared to the previous circuit, but it's a fairly small percentage of the total capacitance).
(https://www.eevblog.com/forum/projects/pulse-current-capacitor-locationplacement/?action=dlattach;attach=160859;image)
In terms of the PCB layout, the capacitors did not move far at all. Maybe a couple of centimeters away from the regulator and closer to the LEDs. Here's part of the layout. I basically moved C3 and C4 right next to R9 and R10. Can anyone explain this? One thing I do notice is that when the capacitors are right after the regulator, and I measure the current from the source (using a 0.1 ohm resistor), I see a lot of oscillation. When the capacitors are moved, I don't see this oscillation anymore. Not sure if it's because the capacitors need to be closer to the LEDs, or if there is something else going on with the large output capacitance and the regulator. I will do some further testing to double check and maybe follow up with some scope screen shots...
(https://www.eevblog.com/forum/projects/pulse-current-capacitor-locationplacement/?action=dlattach;attach=160861;image)
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Considering the piss ant track widths you have for power traces, I'm not surprised you're having problems.
Change those to 1 mm(40 mil) first.
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This is what I changed (I realize this has an extra 4.7uF compared to the previous circuit, but it's a fairly small percentage of the total capacitance).
See the data sheet http://www.ti.com/lit/ds/symlink/lp2989.pdf (http://www.ti.com/lit/ds/symlink/lp2989.pdf), page 17 - 18 and figure 41. Adding the extra 4.7uF made the circuit stable. You just got lucky :) Anyway, just make sure the 4.7uF is low-ESR ceramic meeting the requirements and the voltage rating is at least 15V.
edit: Fixed the data sheet link.
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Considering the piss ant track widths you have for power traces, I'm not surprised you're having problems.
Change those to 1 mm(40 mil) first.
Yes, those traces are small and probably should be beefed up since I have space. They are 12mils wide. However, I'm only running 800mA through for 5us every 26us and during the off times the current is on the order of ~10mA. Even at 800mA, pcb trace width tables state that 12mils is fine for an external trace so I don't think this is contributing to any issues.
This is what I changed (I realize this has an extra 4.7uF compared to the previous circuit, but it's a fairly small percentage of the total capacitance).
See the data sheet http://www.ti.com/lit/ds/symlink/lp2989.pdf (http://www.ti.com/lit/ds/symlink/lp2989.pdf.), page 17 - 18 and figure 41. Adding the extra 4.7uF made the circuit stable. You just got lucky :) Anyway, just make sure the 4.7uF is low-ESR ceramic meeting the requirements and the voltage rating is at least 15V.
The datasheet says it needs a minimum of 4.7uF output capacitance. I have that minimum in both cases. Also, I'm using ceramic caps which do meet the ESR requirements.
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Considering the piss ant track widths you have for power traces, I'm not surprised you're having problems.
Change those to 1 mm(40 mil) first.
Yes, those traces are small and probably should be beefed up since I have space. They are 12mils wide. However, I'm only running 800mA through for 5us every 26us and during the off times the current is on the order of ~10mA. Even at 800mA, pcb trace width tables state that 12mils is fine for an external trace so I don't think this is contributing to any issues.
Sure, but forget the LEDs for a moment and consider the the bulk capacitor recovery requirements.
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Considering the piss ant track widths you have for power traces, I'm not surprised you're having problems.
Change those to 1 mm(40 mil) first.
Yes, those traces are small and probably should be beefed up since I have space. They are 12mils wide. However, I'm only running 800mA through for 5us every 26us and during the off times the current is on the order of ~10mA. Even at 800mA, pcb trace width tables state that 12mils is fine for an external trace so I don't think this is contributing to any issues.
Sure, but forget the LEDs for a moment and consider the the bulk capacitor recovery requirements.
Right. I plan to increase the width in the next revision anyway, but am still surprised that moving the capacitors had such a large effect on whether the pulse current is sourced from the capacitors or the regulator.
Perhaps moving them means a shorter resistance path from the caps and so more current is supplied from them (and potentially because of the small traces, the resistance to the regulator is large)?
I'll play around with adding a series resistor before the capacitors to see if this can further curb the current draw from the source.
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Your narrow traces add inductance increasing impeadance and reducing the effectiveness of your capacitor. Well for 38kHz you would think this isn't overly critical, it depends on the current rise time. You should at the very least increase the trace width between the bypass cap and your switched load reducing the inductance.
Other possible things to try is 33uf and add some lower capacitance caps like maybe 3.3uf and 0.33uf to help with the faster edges. Connect them to a ground plain to reduce inductance. Try adjusting your pulse rise time, you can do this by intentionally slowing the fet by placing increased R between the gate and the driving source. Experiment with that see what happens.
If you plan on another revision consider a proper LC filter and select capacitors to minimze impeadance at the frequency of interest. Just willy nilly banging capacitors in rarely works out well.
OK thanks. I'll do some more testing and see what happens. Thanks everyone for their contributions & advice!