Active loop filter for a PLL, opamp caveats?

[mathias]

Hi all,

I was playing around with an active filter for a PLL I built. The filter was designed with ADISimPLL and built with an ADF4002 PLL chip and SP869 VCO. I never gave much attention to the opamp in the circuit and started out with a OPA227 (low noise, GBW of 8MHz). The loop filter had a designed bandwidth of 10kHz. When I built it up, the output was extremely dirty, not really locking at all. The Vtune signal was a nice triangle though. Then I switched to the LT1115 (GBW of 70MHz) and it would lock, but still a very dirty spectrum on the SA. Adding some caps between output and input of the opamp ameliorated the situation.

Now comes my questions: what are the typical caveats with designing active PLL loop filter that aren't mentioned in the app notes?

[KJDS]

Make sure that the op-amp is decoupled properly. PSRR may well be very high at low frequencies, but will fall as frequency rises. It's worth having a separate regulator for the logic and the op-amp.

Make sure that the inputs and output aren't at the supply rails or you'll run into more problems.

[w2aew]

Don't forget that the loop already has one pole in it.  The loop filter controls the *frequency* of the VCO, but the phase detector that drives the loop filter measures *phase*.  Thus, even if you use a first order filter, the overall loop response is 2nd order.  Thus, watch out for underdamped response, etc.

[moffy]

What I think is happening is that the input products(multiple of input waveform and VCO) have some large high frequency components, so that even though your loop bandwidth is only 10kHz the lower GBW product opamp can't cope. The inverting pin is not being held close to the non inverting pin. You can try and prefilter these components as long as the prefilter is well outside the capture loop frequency.

[mathias]

@w2aew: I would think/hope that the ADISimPLL software would already take this into account. I'm not well educated enough (in the field of EE) to design a filter from scratch, so I have to rely on other peoples calculations. A video by Dave on this subject is highly welcome.

@moffy: I'll play around with the PFD frequency. Currently it was set at 1MHz.

[moffy]

Yeah I have seen the same thing before while designing my own sigma/delta converter. If the products have high frequency components the GBW product of the filter has to be very high.