Author Topic: Trying to get more RAM with very limited pins  (Read 398 times)

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Offline NeywinyTopic starter

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Trying to get more RAM with very limited pins
« on: March 04, 2021, 12:32:29 am »
So I have an STM32H745 nucleo-144 board that I need more RAM on. No problem, thought I, this chip has PSRAM and SDRAM capability. Which is good because I need it to work over the AXI bus. If I could do it in software I would, but I need the FMC to get the commands because I'm using things like the LCD controller which read directly from the AXI bus. However, the LQFP144 pin package doesn't bring out the NCAS line for SDRAM. And I only get 11 pins of PSRAM address lines before I run into things like the USB lines. My understanding is that with PSRAM I only send one address, meaning I'd have a whopping 2K of RAM.

I've been looking to the feasibility of generating the NCAS line using glue logic or a CPLD (I've never worked with a CPLD before so I don't even know if that's a good use for them). It looks from the timing diagram (figure 125/page 907 in https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), I should be able to wait for NRAS, count TRCD, then drop my NCAS line. When SDNE goes back high I bring back up my NCAS line and reset my counter and all that. The thing is, the datasheet's table 89 indicates that they're guaranteeing a 0.5 nS maximum time in dropping NCAS, and frankly I don't know if there's much glue logic out there that can do that kind of nanosecond speed. I've seen maybe 2.5 nS at the bare minimum, which is looking like its in the range of possibility but it'd push it. Especially since the majority of these chips use some low voltages and I think I could get the IO down to 1.8V on this board with a jumper but I don't know for sure and I don't know if the USB and ethernet stuff on the PCB would be compatible with that. So I might need to factor in a level shifter as well.

And this all relies on the SDRAM controller part of the die being in working order. I think it's possible they could've chosen to not break out 1 signal to prevent people from using it if they were getting low yields and needed a way to sell them, I don't know. Seems plausible.

Does any of this seem like a good idea? I don't even know how to test something like this if something goes wrong, I have a multimeter and that's it. I've done around a year with FPGAs so I know my way around and could use one to interface, but it would have to be very high speed and very cheap. Broke college kid and all that.

Thank you.
 


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